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BQ24650 Datasheet, PDF (4/33 Pages) Texas Instruments – Synchronous Switch-Mode Battery Charge Controller for Solar Power With Maximum Power Point Tracking
bq24650
SLUSA75 – JULY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
5.0V ≤ VVCC ≤ 28V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
QUIESCENT CURRENTS
5
28
V
Total battery discharge current (sum of
currents into VCC, BTST, PH, SRP, SRN,
VFB), VFB ≤ 2.1V
VCC < VBAT, VCC > VUVLO (SLEEP)
IBAT
Battery discharge current (sum of currents VCC > VBAT, VCC > VUVLO, CE = LOW
into BTST, PH, SRP, SRN, VFB), VFB ≤
2.1V
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charge done
15 µA
5 µA
5 µA
VCC > VBAT, VCC > VUVLO, CE = LOW
IAC
Adapter supply current (sum of current into
VCC pin)
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, charge done
VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 10nC [1]
0.7
1 mA
2
3 mA
25
mA
CHARGE VOLTAGE REGULATION
VREG
Feedback regulation voltage
Charge voltage regulation accuracy
IVFB
Leakage current into VFB pin
CURRENT REGULATION – FAST CHARGE
TJ = 0°C to 85°C
TJ = –40°C to 125°C
VFB = 2.1 V
–0.5%
-0.7%
2.1
V
0.5%
0.7%
100 nA
VIREG_CHG
SRP-SRN current sense voltage range
Charge current regulation accuracy
CURRENT REGULATION – PRE-CHARGE
VIREG_CHG = VSRP – VSRN
VIREG_CHG = 40 mV
–3%
40
mV
3%
VPRECHG
Precharge current sense voltage range
Precharge current regulation accuracy
CHARGE TERMINATION
VIREG_PRCHG = VSRP – VSRN
VIREG_PRECH = 4 mV
–25%
4
mV
25%
VTERMCHG
Termination current sense voltage range
Termination current accuracy
Deglitch time for termination (both edges)
VITERM = VSRP – VSRN
VITERM = 4 mV
–25%
4
mV
25%
100
ms
tQUAL
Termination qualification time
IQUAL
Termination qualification current
INPUT VOLTAGE REGULATION
VBAT > VRECH and ICHG < ITERM
Discharge current once termination is detected
250
ms
2
mA
VMPPSET
MPPSET regulation voltage
Input voltage regulation accuracy
–0.6%
1.2
V
0.6%
IMPPSET
Leakage current into MPPSET pin
VMPPSET_CD
MPPSET shorted to disable charge
VMPPSET_CE
MPPSET released to enable charge
INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)
VMPPSET = 7 V, TA = 0 – 85°C
1 µA
75 mV
175
mV
VUVLO
AC under-voltage rising threshold
VUVLO_HYS
AC under-voltage hysteresis, falling
VCC LOWV COMPARATOR
Measure on VCC
3.65 3.85
350
4
V
mV
VVCC LOWV_fall
Falling threshold, disable charge
Measure on VCC
VVCC LOWV_rise
Rising threshold, resume charge
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
4.1
V
4.35
V
VSLEEP _FALL
VSLEEP_HYS
SLEEP falling threshold
SLEEP hysteresis
SLEEP rising shutdown deglitch
VVCC – VSRN to enter SLEEP
VCC falling below SRN
40
100
150 mV
500
mV
100
ms
SLEEP falling powerup deglitch
VCC rising above SRN, Delay to exit SLEEP
mode
30
ms
4
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