BQ24650 Datasheet, PDF (15/33 Pages) Texas Instruments – Synchronous Switch-Mode Battery Charge Controller for Solar Power With Maximum Power Point Tracking

bq24650
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SLUSA75 – JULY 2010
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5-A inductor current for
a 10-mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is
break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where
both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the
low-side FET turn on keeps power dissipation low, and allows safe charging at high currents. During
synchronous mode the inductor current is always flowing and the converter operates in continuous conduction
mode (CCM), creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5-A inductor
current for a 10-mΩ sense resistor). In addition, the charger is forced into non-synchronous mode when battery
voltage is lower than 2V or when the average SRP-SRN voltage is lower than 1.25mV.
During non-synchronous operation, the body-diode of the low-side MOSFET can conduct the positive inductor
current after the low-side n-channel power MOSFET turns off. When the load current decreases and the inductor
current drops to zero, the body diode is naturally turned off and the inductor current becomes discontinuous. This
mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel power MOSFET
turns on when the bootstrap capacitor voltage drops below 4.2V, then the low-side power MOSFET turns off and
stays off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The
low-side MOSFET on time is required to ensure the bootstrap capacitor is always recharged and able to keep the
high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular
dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current. The
low-side pulse pulls the PH node (connection between high and low-side MOSFETs) down, allowing the
bootstrap capacitor to recharge up to the REGN LDO value. After the refresh pulse, the low-side MOSFET is
kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the recharge pulse. The charge should be low enough to be absorbed by the input capacitance.
Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the
low-side MOSFET does not turn on (except for recharge pulse) either, and there is almost no discharge from the
battery.
During DCM mode the loop response automatically changes and has a single pole system at which the pole is
proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
CYCLE-BY-CYCLE CHARGE UNDER CURRENT
In the bq24650, if the SRP-SRN voltage decreases below 5mV, the low side FET is turned off for the remainder
of the switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on when the
bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap capacitor. This is
important to prevent negative inductor current from causing a boost effect in which the input voltage increases as
power is transferred from the battery to the input capacitors and lead to an over-voltage stress on the VCC node
and potentially cause damage to the system.
INPUT OVER-VOLTAGE PROTECTION (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled.
INPUT UNDER-VOLTAGE LOCK OUT (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either input adapter or battery, since a conduction path exists from the battery to VCC through the high-side
NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC, including VREF LDO, are
disabled.
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