BQ24650 Datasheet, PDF (25/33 Pages) Texas Instruments – Synchronous Switch-Mode Battery Charge Controller for Solar Power With Maximum Power Point Tracking

bq24650
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SLUSA75 – JULY 2010
PCB LAYOUT
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high frequency current path loop (see Figure 24) is important to prevent electrical
and magnetic field radiation and high frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place input capacitor as close as possible to the switching MOSFET supply and ground connections and use
the shortest copper trace connection. These parts should be placed on the same layer of the PCB instead of
on different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals, and the gate drive signal traces
kept short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize
loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection
for best current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route analog ground separately from power ground and use a single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Connect analog ground to the GND pin. Use the thermal
pad as a single ground connection point to connect analog ground and power ground together, or use a 0-Ω
resistor to tie analog ground to power ground (thermal pad should tie to analog ground in this case). A
star-connection under the thermal pad is highly recommended.
8. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
10. The number and physical size of the vias should be enough for a given current path.
SW
L1
R1
V_BAT
High
V_IN
Frequency
Current
BAT
C1
Path
PGND
C2
C3
Figure 24. High Frequency Current Path
Copyright © 2010, Texas Instruments Incorporated
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