BQ24650 Datasheet, PDF (14/33 Pages) Texas Instruments – Synchronous Switch-Mode Battery Charge Controller for Solar Power With Maximum Power Point Tracking

bq24650
SLUSA75 – JULY 2010
ENABLE AND DISABLE CHARGING
The following conditions have to be valid before charging is enabled:
• Charge is allowed (MPPSET > 175mV)
• Device is not in Under-Voltage-Lock-Out (UVLO) mode and VCC is above the V_CCLOWV threshold
• Device is not in SLEEP mode (i.e. VCC > SRN)
• VCC voltage is lower than AC over-voltage threshold (VCC < VACOV)
• 30ms delay is complete after initial power-up
• REGN LDO and VREF LDO voltages are at correct levels
• Thermal Shut (TSHUT) is not valid
• TS fault is not detected
One of the following conditions stops on-going charging:
• Charge is disabled (MPPSET < 75mV)
• Adapter is removed, causing the device to enter V_CCLOWV or SLEEP mode
• Adapter voltage is less than 100mV above battery
• Adapter is over voltage
• REGN or VREF LDO voltage is not valid
• TSHUT IC temperature threshold is reached
• TS voltage goes out of range indicating the battery temperature is too hot or too cold
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AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts approximately 1.6ms, for a typical rise time of 13ms. No external components are needed for this
function.
CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter must be selected to give a resonant frequency of 12 kHz – 17 kHz for the bq24650,
where resonant frequency, f_o, is given by:
1
f_o =
2p L_oC_o
(6)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop
compensation. The ramp is offset by 300mV in order to allow zero percent duty-cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100%
duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the
N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below
4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side
n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the
high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again
due to leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.
14
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