BQ24180 Datasheet, PDF (4/39 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and Accessory Power Connection

bq24180
SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of Figure 2, V_VBUS = 5V, HZ_MODE=0, CD=0, T_J = –40°C to 125°C and T_J = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
V_{IN_DPM}
The threshold when input based DPM loop
kicks in
Charge mode, programmable
4.15
4.71 V
DPM loop kick-in threshold tolerance
–2%
2%
FAULTY ADAPTER PROTECTION
V_{VBUS (MIN)}
Faulty adapter threshold
Deglitch time for Faulty adapter
3.6
3.8
4.0 V
30
ms
Hysteresis for faulty adapter protection
Current source for faulty adapter protection
V_VBUS Rising
100
200 mV
20
30
40 mA
t_INT
Detection Interval
INPUT CURRENT LIMITING
2
s
I_{IN_LIMIT}
DCOUT
Input current limiting threshold
USB charge mode, current
pulled from PMID
I_{IN_LIMIT} = 100 mA
I_{IN_LIMIT} = 500 mA
I_{IN_LIMIT} = 800 mA
90
95
100
450
475
500 mA
700
755
800
R_DCOUT
I_{LIM_DCOUT}
t_{DGL_DCOUT}
DCOUT Pass FET on-resistance
DCOUT current limit programmable range
I_DCOUT = 500 mA
Programmable via I²C
Deglitch time from DCOUT current-limit event
to DCOUT latch-off
300 mΩ
350
1400 mA
14.5
ms
I_{LIM_DCOUT}
DCOUT current limit range
BATTERY RECHARGE THRESHOLD
I_{LIM_DCOUT} = 350mA
270
350
Programmable via I²C
I_{LIM_DCOUT} = 750mA
650
750
mA
I_{LIM_DCOUT} = 1050mA
800 1050
I_{LIM_DCOUT} = 1400mA
1050 1400
V_RCH
Recharge threshold voltage
Deglitch time
STAT OUTPUTS
Below VOREG
V_CSOUT decreasing below threshold,
t_FALL = 100 ns, 10-mV overdrive
100
120
150 mV
130
ms
V_OL(STAT)
Low-level output saturation voltage, STAT
High-level leakage current
I_O = 10 mA, sink current
Voltage on STAT pin is 5V
0.5 V
1 µA
V_OL(INT)
Low-level output saturation voltage, INT
High-level leakage current
I_O = 1 mA, sink current
Voltage on INT pin is 5V
0.4 V
1 µA
I²C BUS LOGIC LEVELS AND TIMING CHARACTERISTICS
V_OL
Output low threshold level
Input low threshold level
Input high threshold level
I_(bias)
Input bias current
f_SCL
SCL clock frequency
SLEEP COMPARATOR
I_O = 10 mA, sink current
V_(pull-up) = 1.8 V, SDA and SCL
V_(pull-up) = 1.8 V, SDA and SCL
V_(pull-up) = 1.8 V, SDA and SCL
0.4 V
0.4 V
1.2
V
1 µA
3.4 MHz
V_SLP
V_SLP-EXIT
UVLO
Sleep-mode entry threshold,
V_BUS-V_CSOUT
Sleep-mode exit hysteresis
Deglitch time for VBUS rising above
V_SLP+V_{SLP_EXIT}
2.3 V ≤ V_CSOUT ≤ V_OREG, V_VBUS falling
2.3 V ≤ V_CSOUT < V_OREG
Rising voltage, 2-mV over drive, t_RISE = 100 ns
0
40
100 mV
140
200
260 mV
30
ms
V_UVLO
V_{UVLO_HYS}
PWM
IC active threshold voltage
IC active hysteresis
V_VBUS rising
V_VBUS falling from above V_UVLO
3.05
3.3 3.55 V
120
150
mV
Internal top reverse blocking MOSFET
on-resistance
I_{IN_LIMIT} = 500 mA, Measured from V_VBUS to PMID
110
210 mΩ
Internal top N-channel Switching MOSFET
on-resistance
Measured from PMID to SW
130
250 mΩ
4
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