BQ24180 Datasheet, PDF (23/39 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and Accessory Power Connection

bq24180
www.ti.com
SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010
Input Voltage Protection in Charge Mode
Sleep Mode
The bq24180 enters the low-power sleep mode if the voltage on V_VBUS falls below sleep-mode entry
threshold, V_CSOUT+V_SLP, and V_VBUS is higher than the undervoltage lockout threshold, V_UVLO. This feature
prevents draining the battery during the absence of V_VBUS. During sleep mode, both the reverse blocking
switch Q1 and PWM are turned off. Once the input rises above the sleep threshold, the device returns to
normal operation.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, VBUS voltage will decease. Once the VBUS drops to V_{VBUS_LOW} (default 4.76V), the charge
current is tapered down to prevent the further drop of VBUS. When the IC enters this mode, the charge
current is lower than the set value and the DPM_STATUS bit is set (B4 in Register 05H). This feature
ensures IC compatibility with adapters with different current capabilities.
Faulty Adapter Detection
When an input source is connected to the bq24180, the device enter faulty adapter detection mode. In this
mode, the IC sources 30mA to the battery for t_INT. After t_INT, the input voltage is monitored. If V_VBUS>V_IN(MIN),
the device continues the startup sequence. If V_VBUS<V_IN(MIN), a single 128µs pulse is sent on the STAT and
INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I²C and the process
repeats until a good adapter is detected.
High-Input and Input Over-Voltage Protection
The bq24180 provides two levels over-voltage protection on the input. A high-input comparator disables the
PWM operation and sources the 50mA precharge current to the battery when V_HIGH < V_VBUS < V_OVP. This
allows for unregulated adapters to be used. The 50mA pulls the adapter voltage down to the usable voltage
and then normal operation begins.
The built-in input over-voltage protection to protect the device and other components against damage from
overvoltage on the input supply (Voltage from V_VBUS to PGND). When V_VBUS > V_OVP, the bq24180 latches off
the PWM converter, a single 128µs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x
bits of the status registers are updated in the I²C. Once the OVP fault is removed, the STATx and FAULT_x
bits are cleared and the device returns to normal operation.
Charge Status Outputs (STAT, INT)
The STAT and INT outputs are used to indicate operation conditions for bq24180. STAT and INT are pulled low
during charging when EN_STAT bit in the control register (00H) is set to “1”. When charge is complete or
disabled, INT and STAT are high impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify
the host. The status of STAT and INT during different operation conditions is summarized in Table 1. STAT
drives an LED for visual indication. INT is available for connecting to the logic rail for host communication.
Table 1. STAT Pin Summary
CHARGE STATE
Charge in progress and EN_STAT=1
Other normal conditions
Charge mode faults: Timer fault, sleep mode,
VBUS over voltage, VBUS UVLO, thermal
shutdown
STAT and INT BEHAVIOR
Low
Open-drain
128-µs pulse, then open-drain
Control Bits in Charge Mode
CE Bit (Charge Enable)
The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this
bit enables the charge and a high logic level (1) disables the charge.
RESET Bit
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): bq24180
Submit Documentation Feedback
23