BQ24180 Datasheet, PDF (26/39 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and Accessory Power Connection

bq24180
SLUSA02 A – FEBRUARY 2010 – REVISED FEBRUARY 2010
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receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 35). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in a incorrect state. Attempting to read data from register addresses not listed in
this section will result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
START
Condition
Not Acknowledge
Acknowledge
Figure 35. Acknowledge on the I2C Bus
Clock Pulse for
Acknowledgement
Figure 36. Bus Protocol
F/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'.
This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.
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