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ADS5560 Datasheet, PDF (4/53 Pages) Texas Instruments – 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS
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ADS5560
ADS5562
SLWS207 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling rate = Max Rated, sine wave input clock, 1.5 VPP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB).
Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = DRVDD = 3.3 V, sampling
rate = Max Rated, unless otherwise noted.
PARAMETER
TEST
CONDITIONS
ADS5562
MIN
TYP
MAX MIN
RESOLUTION
16
ANALOG INPUT
Differential input voltage
range (1)
3.56
Differential input
5
capacitance
Analog input bandwidth
300
Analog input common
6.6
mode current (per input pin)
VCM
Common mode output
Internal reference
1.5
voltage
mode
VCM output current
Internal reference
±4
capability
mode
DC ACCURACY
No Missing Codes
0 dB gain
Assured
DNL
Differential non-linearity
-0.95
0.5
3
-0.95
INL
Integral non-linearity
-8.5
±3
8.5
-8.5
Offset error
-25
±10
25
-25
Offset error temperature
coefficient
0.005
Variation of offset error
1.5
across AVDD supply
There are two sources of gain error: i) internal reference inaccuracy and ii) channel gain
error
EGREF
Gain error due to internal
reference inaccuracy alone
-2.5
±1
2.5
-2.5
ECHAN
Channel gain error alone
Channel gain error
temperature coefficient
-2.5
±1
2.5
-2.5
0.01
POWER SUPPLY
IAVDD
Analog supply current
210
250
IDRVDD
Digital supply current
CL = 5 pF
Total power
LVDS mode
IO = 3.5 mA, RL =
100 Ω
CMOS mode
FIN = 3 MHz
LVDS mode
52
60
865
1100
Standby power
STANDBY mode
155
with clock running
Clock stop power
125
150
ADS5560
TYP
16
3.56
5
300
6.6
1.5
±4
Assured
0.5
±3
±10
0.005
1.5
±1
±1
0.01
160
44
37
674
135
125
MAX
3
8.5
25
2.5
2.5
190
810
150
UNIT
bits
VPP
pF
MHz
µA/MSPS
V
mA
LSB
LSB
mV
mV/°C
mV/V
%FS
%FS
Δ%/°C
mA
mA
mA
mW
mW
mW
(1) The full-scale voltage range is a function of the fine gain settings. See Table 23.
4
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