ADS5560 Datasheet, PDF (30/53 Pages) Texas Instruments – 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS

ADS5560
ADS5562
SLWS207 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 V_PP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
86
85
84
83
82
81
80
79
78
0
SNR vs Fin, 0 dB gain
LVDS
CMOS
5
10
15
20
25
f_IN − Input Frequency − MHz
Figure 30.
30
G027
100
98
96
94
92
90
88
86
84
82
80
0
SFDR Across Fine Gain
Input adjusted to get −1dBFS input
3 dB
2 dB
6 dB
5 dB
4 dB
0 dB
1 dB
5
10
15
20
25
f_IN − Input Frequency − MHz
Figure 32.
30
G030
Performance vs AV_DD Supply
98
96
f_IN = 5.01 MHz
DRV_DD = 3.3 V
94
SFDR
92
90
88
86
SNR
84
82
3.0
3.1
3.2
3.3
3.4
3.5
AV_DD − Supply Voltage − V
Figure 34.
90
89
88
87
86
85
84
83
82
3.6
G034
SFDR vs Fin
96
92
88
84
80
76
0
5
10
15
20
25
f_IN − Input Frequency − MHz
Figure 31.
30
G028
87
86
85
84
83
82
81
80
79
78
77
0
SNR Across Fine Gain
2 dB
Input adjusted to get −1dBFS input
0 dB
3 dB
1 dB
4 dB
5
5 dB _{6 dB}
10
15
20
25
f_IN − Input Frequency − MHz
Figure 33.
30
G031
Performance vs DRV_DD Supply
100
f_IN = 5.01 MHz
98 _{AVDD = 3.3 V}
96
94
SFDR
92
90
88
SNR
86
84
3.0
3.1
3.2
3.3
3.4
3.5
DRV_DD − Supply Voltage − V
Figure 35.
90
89
88
87
86
85
84
83
82
3.6
G035
30
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5560 ADS5562