ADS5560 Datasheet, PDF (18/53 Pages) Texas Instruments – 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS

ADS5560
ADS5562
SLWS207 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
A7 - A0 (hex)
D7
D6
<STBY>
63
GLOBAL
POWER
DOWN
Table 12.
D5
D4
D3
D2
D1
D0
<DF>
DATA
FORMAT
2's COMP or
OFFSET
BINARY
<LOW SPEED>
ENABLE LOW
SAMPLING
FREQUENCY
OPERATION
D3
<DF> Output Data Format
0
2's complement
1
Offset binary
D0
<LOW SPEED> Low Sampling Frequency Operation
0
DEFAULT SPEED mode (for Fs > 30 MSPS)
1
LOW SPEED mode eabled (for Fs ≤ 30 MSPS)
D7
<STBY> Global STANDBY
0
Normal operation
1
Global power down (includes ADC, internal references and output buffers)
A7 - A0 (hex)
65
D7
D6
D5
<TEST PATTERNS> — ALL 0S, ALL 1s,
TOGGLE, RAMP, CUSTOM PATTERN
Table 13.
D4
D3
D2
D1
D0
D7 - D5
000
001
010
011
100
101
111
<TEST PATTERN> Outputs selected test pattern on data lines
Normal operation
All 0s
All 1s
Toggle pattern - alternate 1s and 0s on each data output and across data
outputs
Ramp pattern - Output data ramps from 0x0000 to 0xFFFF by one code
every clock cycle
Custom pattern - Outputs the custom pattern in CUSTOM PATTERN
registers A and B
Unused
18
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