ADS5560 Datasheet, PDF (31/53 Pages) Texas Instruments – 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS

ADS5560
ADS5562
www.ti.com ....................................................................................................................................................................................................... SLWS207 – MAY 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = Max Rated, sine wave input clock, 1.5 V_PP clock
amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, DDR LVDS interface, default fine
gain (1dB), (unless otherwise noted)
Performance vs Temperature
98
88
f_IN = 10.1 MHz
96
87
SFDR
94
86
92
85
90
SNR
84
88
83
86
−40 −20
0
20
40
60
T − Temperature − °C
Figure 36.
82
80
G036
Performance vs Clock Amplitude
94
88
92 ^{fIN = 10.1 MHz}
87
90
SFDR
86
88
85
86
84
84
SNR
83
82
82
80
81
78
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Input Clock Amplitude − V_PP
G038
Figure 38.
Output Noise Histogram
40
RMS (LSB) = 1.429
35
30
25
20
15
10
5
0
Output Code
G040
Figure 40.
Performance vs Input Amplitude, 0 dB gain
120
91
110
SFDR (dBFS)
89
100
87
90
SNR (dBFS)
85
80
83
70 _{SFDR (dBc)}
81
60
79
50
77
f_IN = 5.01 MHz
40
75
−60
−50
−40
−30
−20
−10
0
Input Amplitude − dBFS
G037
Figure 37.
Performance vs Clock Duty Cycle
100
86
f_IN = 5.01 MHz
SFDR
96
84
92
SNR
82
88
80
84
78
80
76
76
35
40
45
50
55
60
Input Clock Duty Cycle − %
Figure 39.
74
65
G039
Performance in External Reference Mode
92
87
f_IN = 5.01 MHz
External Reference Mode
90
86
SFDR
88
85
86
84
SNR
84
83
82
82
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
V_VCM − VCM Voltage − V
G041
Figure 41.
Copyright © 2008, Texas Instruments Incorporated
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