TMS320F206_06 Datasheet, PDF (39/58 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
CI
CLKR
CLKX
CO
D
FR
FX
H
HA
IN
IO
Address or A [15 : 0]
CLKIN / X2
Serial-port receive clock
Serial-port transmit clock
CLKOUT1
Data or D [15:0]
FSR
FSX
HOLD
HOLDA
INTN; BIO, INT1 – INT3, NMI
IOx : IO0, IO1, IO2, or IO3
M
Address, data, and control signals:
(A, D, MS, S, BR, RD, W, and R/W)
MS
Memory strobe pins IS, DS, or PS
R
READY
RD
Read cycle or RD
RS
RESET pins RS or RS
S
STRB or Synchronous
TP
Transitory phase
W
Write cycle or WE
Lowercase subscripts and their meanings are:
a
access time
c
cycle time (period)
d
delay time
dis
disable time
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
The following letters and symbols and their meanings are:
H
High
L
Low
IV
Invalid
HZ
High impedance
X
Unknown, changing, or don’t care level
general notes on timing parameters
All output signals from the TMS320x20x devices (including CLKOUT1) are specified from an internal clock such
that all output transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
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