TMS320F206_06 Datasheet, PDF (19/58 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSOR

TMS320F206
DIGITAL SIGNAL PROCESSOR
on-chip registers (continued)
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
Table 8. On-Chip Memory and I/O Mapped Registers
NAME
ADDRESS
VALUE AT
RESET†
DESCRIPTION
Interrupt mask register. This 7-bit register individually masks or enables the seven
interrupts. Bit 0 shares external interrupt INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2
ties to the timer interrupt, TINT. Bits 3 and 4, RINT and XINT, respectively, are for the
IMR
DS@0004
0000h
synchronous serial port, SSP. Bit 5, TXRXINT, shares the transmit and receive interrupts for
the asynchronous serial port, ASP. Bit 6 is reserved for monitor mode emulation operations
and must always be set to 0 except in conjunction with emulation monitor operations.
Bits 7 – 15 are not used in the TMS320F206.
GREG
DS@0005
0000h
Global memory allocation register. This 8-bit register specifies the size of the global memory
space. GREG is set to 0 at reset.
Interrupt flag register. The 7-bit IFR indicates that the TMS320F206 has latched an interrupt
from one of the seven maskable interrupts. Bit 0 shares external interrupt INT1 and HOLD.
INT2 and INT3 share bit 1. Bit 2 ties to the timer interrupt, TINT. Bits 3
and 4, RINT and XINT, respectively, are for the synchronous serial port, SSP. Bit 5, TXRXINT
IFR
DS@0006
0000h
shares the transmit and receive interrupts for the asynchronous serial port, ASP. Bit 6 is
reserved for monitor-mode emulation operations and must always be set to 0 except in
conjunction with emulation monitor operations. Writing a 1 to the respective interrupt bit
clears an active flag and the respective pending interrupt. Writing a 1 to an inactive flag has
no effect. Bits 7 – 15 are not used in the TMS320F206.
F_ACCESS0 IS@FFE0
0001h
FLASH 0 access-control register. Bit 0 selects one of two possible access modes for
FLASH 0. All other bits are reserved. If bit 0 is cleared to 0, register-access mode is selected.
For a detailed description of register-access mode, refer to the TMS320F20x/F24x DSPs
Embedded Flash Memory Technical Reference (literature number SPRU282) available
during 2nd quarter of 1998. If bit 0 is set to a 1, array-access mode is selected. In
array-access mode, FLASH 0 memory array is mapped to the address range of FLASH 0.
F_ACCESS0 is set to 0x0001h at reset.
F_ACCESS1 IS@FFE1
0001h
FLASH 1 access-control register. Bit 0 selects one of two possible access modes for
FLASH 1. All other bits are reserved. If bit 0 is cleared to 0, register-access mode is selected.
For a detailed description of register-access mode, refer to the TMS320F20x/F24x DSPs
Embedded Flash Memory Technical Reference (literature number SPRU282) available
during 2nd quarter of 1998. If bit 0 is set to a 1, array-access mode is selected. In
array-access mode, FLASH 1 memory array is mapped to the address range of FLASH 1.
F_ACCESS1 is set to 0x0001h at reset.
PMST
IS@FFE4
0006h
Bit 0 latches in the MP/MC pin at reset. This bit can be written to configure
Microprocessor (1) or Microcontroller mode (0). Bits 1 and 2 configure the SARAM
mapping either in program memory, data memory, or both. At reset, these bits are 11, the
SARAM is mapped in both program and data space.
DON (bit 2)
PON (bit 1)
0
0
- SARAM not mapped, address in external
memory
0
1
- SARAM in on-chip program memory at 0x8000h
1
0
SARAM in on-chip data memory at 0x800h
1
1
SARAM in on-chip program and data memory
(reset value)
Bit 15 – Fast RD, FRDN. This bit provides software control to select an inverted R/W
signal in place of the RD signal (pin 45). This is intended to help achieve zero wait-state
memory interface with slow memory devices. At reset, this bit is 0 and selects RD as the
signal at pin 45. If the FRDN bit is written with a 1, pin 45 is replaced with the inverted
R/W signal.
CLK
IS@FFE8
0000h
CLKOUT1 on or off. At reset, bit 0 is configured as a zero for the CLKOUT1 pin to be active.
If bit 0 is a 1, CLKOUT1 pin is turned off.
† _{‘x’ indicates undefined or value based on the pin levels at reset.}
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