TMS320VC549_06 Datasheet, PDF (38/63 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004
reset, BIO, interrupt, and MP/MC timings
timing requirements over recommended operating conditions for reset, interrupt, BIO, and MP/MC
[H = 0.5 t_c(CO)] (see Figure 15, Figure 16, and Figure 17)
549-80
549-100
549-120
MIN MAX MIN MAX MIN MAX
UNIT
th(RS)
Hold time, RS after CLKOUT low
0
0
0
ns
th(BIO)
th(INT)
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low†
0
0
0
0
0
ns
0
ns
th(MPMC)
tw(RSL)
Hold time, MP/MC after CLKOUT low
Pulse duration, RS lowद
0
0
0
ns
4H + 7
4H+5
4H+5
ns
tw(BIO)S
Pulse duration, BIO low, synchronous
2H+7
2H+5
2H+5
ns
tw(BIO)A
Pulse duration, BIO low, asynchronous
4H
4H
4H
ns
tw(INTH)S
Pulse duration, INTn, NMI high (synchronous)
2H+7
2H+7
2H+7
ns
tw(INTH)A
Pulse duration, INTn, NMI high (asynchronous)
4H
4H
4H
ns
tw(INTL)S
Pulse duration, INTn, NMI low (synchronous)
2H+7
2H+7
2H+7
ns
tw(INTL)A
Pulse duration, INTn, NMI low (asynchronous)
4H
4H
4H
ns
tw(INTL)WKP Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
10
8
tsu(RS)
Setup time, RS before X2/CLKIN low§
5
5
8
ns
5
ns
tsu(BIO)
Setup time, BIO before CLKOUT low
10 2H
9
2H
8
2H ns
tsu(INT)
Setup time, INTn, NMI, RS before CLKOUT low
10 2H
9
2H
8
2H ns
tsu(MPMC)
Setup time, MP/MC before CLKOUT low
10
8
8
ns
† _{The external interrupts (INT0 −INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs}
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1−0−0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
‡ _{If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to assure synchronization}
and lock-in of the PLL.
§ _{Divide-by-two mode}
¶ _{Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section).}
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