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TMS320VC549_06 Datasheet, PDF (25/63 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR | |||
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TMS320VC549
FIXEDÄPOINT DIGITAL SIGNAL PROCESSOR
memory and parallel I/O interface timing (continued)
SPRS078G â SEPTEMBER 1998 â REVISED OCTOBER 2004
switching characteristics over recommended operating conditions for a parallel I/O port read
(IOSTRB = 0)â â¡ (see Figure 7)
PARAMETER
549-80
MIN MAX
td(CLKL-A)
Delay time, address valid from CLKOUT low
â1
5
td(CLKH-ISTRBL) Delay time, IOSTRB low from CLKOUT high
0
5
td(CLKH-ISTRBH) Delay time, IOSTRB high from CLKOUT high
â1
5
th(A)IOR
Hold time, address after CLKOUT low
â1
5
â Address and IS timings are included in timings referenced as address.
â¡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.
549-100
MIN MAX
â1
4
0
4
â1
4
â1
4
549-120
MIN MAX
â1
4
0
4
â1
4
â1
4
UNIT
ns
ns
ns
ns
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25
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