TMS320VC549_06 Datasheet, PDF (16/63 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC549
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004
divide-by-two/divide-by-four clock option − PLL disabled
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions for divide-by-two/
divide-by-four clock option − PLL disabled [H = 0.5t_c(CO)] (see Figure 2 and Figure 3, and the
recommended operating conditions table)
PARAMETER
549-80
MIN TYP
MAX
549-100
MIN TYP MAX
549-120
MIN TYP MAX
UNIT
tc(CO)
Cycle time, CLKOUT
12.5‡ 2tc(CI)
† _{10‡ 2tc(CI)}
† _{8.33‡ 2tc(CI)}
† _ns
td(CIH-CO)
Delay time, X2/CLKIN high to
CLKOUT high/low
3
6
10
3
6
10
3
6
10 ns
tf(CO)
Fall time, CLKOUT†
2
2
2
ns
tr(CO)
Rise time, CLKOUT†
2
2
2
ns
tw(COL)
Pulse duration, CLKOUT low†
H−3 H−1
H H−2 H−1
H H−2 H−1
H ns
tw(COH)
Pulse duration, CLKOUT high†
H−3 H−1
H H−2 H−1
H H−2 H−1
H ns
† _{This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies}
approaching 0 Hz.
‡ _{It is recommended that the PLL clocking option be used for maximum frequency operation.}
16
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443