MSC1211 Datasheet, PDF (37/105 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory

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ACCESSING EXTERNAL MEMORY
If external memory is used, P0 and P2 must be configured
as address and data lines. If external memory is not used, P0
and P2 can be configured as general-purpose I/O lines
through the hardware configuration register (HCR0, HCR1).
To enable access to external memory, bits 0 and 1 of the
HCR1 register must be set to ‘0’. When these bits are
enabled all memory accesses for both internal and
external memory will appear on Ports 0 and 2. During the
data portion of the cycle for internal memory, Port 0 will be
zero for security purposes.
Accesses to external memory are of two types: to external
Program Memory and to external Data Memory. Accesses
to external Program Memory use signal PSEN (program
store enable) as the read strobe. Accesses to external
Data Memory use RD or WR (alternate functions of P3.7
and P3.6) to strobe the memory.
If desired, External Program Memory and external Data
Memory may be combined by applying the RD and PSEN
signals to the inputs of an AND gate and using the output
of the gate as the read strobe to the external Program/Data
Memory.
A program fetch from external Program Memory uses a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOVX @DPTR) or an 8-bit
address (MOVX @R_I).
If Port 2 is selected for external memory use (HCR1, bit 0),
it cannot be used as general-purpose I/O. This bit (or Bit
1 of HCR1) also forces bits P3.6 and P3.7 to be used for
WR and RD instead of I/O. Port 2, P3.6, and P3.7 should
all be written to ‘1.’
If an 8-bit address is being used (MOVX @R_I), the contents
of the MPAGE (92h) SFR remain at the Port 2 pins
throughout the external memory cycle, which facilitates
paging.
In any case, the low byte of the address is time-multiplexed
with the data byte on Port 0. The ADDR/DATA signals use
CMOS drivers in the Port 0, Port 2, WR, and RD output
buffers. Thus, in this application, the Port 0 pins are not
open-drain outputs, and do not require external pull-ups for
high-speed access. Signal ALE (Address Latch Enable)
should be used to capture the address byte into an external
latch. The address byte is valid at the negative transition
of ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is activated, and remains
there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at Port 0 just before the read
strobe is deactivated.
MSC1211, MSC1212
MSC1213, MSC1214
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
The functions of Port 0 and Port 2 are selected in HCR1.
(Hardware configuration registers can only be changed
during Flash Programming mode.) The default state is for
Port 0 and Port 2 to be used as general-purpose I/O. If an
external memory access is attempted when they are
configured as general-purpose I/O, the values of Port 0
and Port 2 will not be affected.
External Program Memory is accessed under two conditions:
1. Whenever signal EA is low during reset, then all future
code and data accesses are external; or
2. Whenever the Program Counter (PC) contains a
number that is outside of the internal Program Memory
address range, if the ports are enabled.
If Port 0 and Port 2 are selected for external memory, all 8
bits of Port 0 and Port 2, as well as P3.6 and P3.7, are
dedicated to an output function and may not be used for
general-purpose I/O. During external program fetches,
Port 2 outputs the high byte of the PC.
Programming Flash Memory
There are four sections of Flash Memory for programming:
1. 128 configuration bytes.
2. Reset sector (4kB) (not to be confused with the 2kB
Boot ROM).
3. Program Memory.
4. Data Memory.
Boot ROM
There is a 2kB Boot ROM that controls operation during
serial or parallel programming. Additionally, the Boot ROM
routines can be accessed during the user mode if it is
enabled. When enabled, the Boot ROM routines will be
located at memory addresses F800h−FFFFh during user
mode. In program mode the Boot ROM is located in the first
2kB of Program Memory. For additional information, refer
to Application Note SBAA085, available for download from
the TI web site (www.ti.com).
The MSC1211/12/13/14 are shipped with Flash Memory
erased (all 1s). Parallel programming methods typically
involve a third-party programmer. Serial programming
methods typically involve in-system programming. UAM
allows Code Program and Data Memory programming.
The actual code for Flash programming cannot execute
from Flash. That code must execute from the Boot ROM
or internal (von Neumann) RAM.
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