MSC1211 Datasheet, PDF (24/105 Pages) Texas Instruments – Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory

MSC1211, MSC1212
MSC1213, MSC1214
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
ENHANCED 8051 CORE
All instructions in the MSC1211/12/13/14 families perform
exactly the same functions as they would in a standard
8051. The effects on bits, flags, and registers is the same;
however, the timing is different. The MSC1211/12/13/14
families utilize an efficient 8051 core which results in an
improved instruction execution speed of between 1.5 and
3 times faster than the original core for the same external
clock speed (4 clock cycles per instruction versus 12 clock
cycles per instruction, as shown in Figure 9). This
efficiency translates into an effective throughput
improvement of more than 2.5 times, using the same code
and same external clock speed. Therefore, a device
frequency of 40MHz for the MSC1211/12/13/14 actually
performs at an equivalent execution speed of 100MHz
compared to the standard 8051 core. This increased
performance allows the the device to be run at slower
external clock speeds, which reduces system noise and
power consumption, but provides greater throughput. This
performance difference can be seen in Figure 10. The
timing of software loops will be faster with the
MSC1211/12/13/14. However, the timer/counter operation
of the MSC1211/12/13/14 may be maintained at 12 clocks
per increment, or optionally run at 4 clocks per increment.
The MSC1211/12/13/14 also provide dual data pointers
(DPTRs) to speed block Data Memory moves.
Additionally, both devices can stretch the number of
memory cycles to access external Data Memory from
between two and nine instruction cycles in order to
accommodate different speeds of memory or devices, as
shown in Table 2. The MSC1211/12/13/14 provide an
external memory interface with a 16-bit address bus (P0
and P2). The 16-bit address bus makes it necessary to
multiplex the low address byte through the P0 port. To
enhance P0 and P2 for high-speed memory access,
hardware configuration control is provided to configure the
ports for external memory/peripheral interface or
general-purpose I/O.
www.ti.com
Single-Byte, Single-Cycle
Instruction
ALE
PSEN
AD0−AD7
PORT 2
CLK
ALE
PSEN
AD0−AD7
PORT 2
4 Cycles
12 Cycles
Single-Byte, Single-Cycle
Instruction
Figure 10. Comparison of MSC1211/12/13/14
Timing to Standard 8051 Timing
CKCON
(8Eh)
MD2:MD0
000
001
010
011
100
101
110
111
INSTRUCTION
CYCLES
(for MOVX)
2
3 (default)
4
5
6
7
8
9
RD or WR
STROBE
WIDTH
(SYS CLKs)
2
4
8
12
16
20
24
28
RD or WR
STROBE
WIDTH
(µs) AT 12MHz
0.167
0.333
0.667
1.000
1.333
1.667
2.000
2.333
Table 2. Memory Cycle Stretching (stretching of
MOVX timing as defined by MD2, MD1, and MD0
bits in CKCON register at address 8Eh).
CLK
instr_cycle
n+1
n+2
cpu_cycle
C1
C2
C3
C4
C1
C2
C3
C4
C1
Figure 9. Instruction Timing Cycle
24