TMS320F28069 Datasheet, PDF (31/159 Pages) Texas Instruments – Piccolo Microcontrollers

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TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011
3.5 Brief Descriptions
3.5.1 CPU
The 2806x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The
C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level
language, but also enabling development of math algorithms using C/C++. The device is as efficient at
MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This
efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit
processing capabilities enable the controller to handle higher numerical resolution problems efficiently.
Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. The device has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at
high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
3.5.2 Control Law Accelerator (CLA)
The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the
capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its
own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be
specified. Each task is started by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0.
The CLA executes one task at a time to completion. When a task completes the main CPU is notified by
an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA
can directly access the ADC Result registers and the ePWM+HRPWM registers. Dedicated message
RAMs provide a method to pass additional data between the main CPU and the CLA.
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Device Overview
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Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062