DRV3203-Q1_15 Datasheet, PDF (31/37 Pages) Texas Instruments – Three-Phase Brushless Motor Driver

DRV3203-Q1
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Table 12. Electrical Characteristics
PARAMETER
CONDITIONS
VB = 12 V, T_A = –40°C to +125℃ (unless otherwise specified)
Input Buffer1
V_IH
V_IL
Ru or Rd
Input threshold logic high
Input threshold logic low
Input pullup or pulldown resistance
Output Buffer1(2)
V_OH
Output level logic high
V_OL
Output level logic low
Output Buffer3
Isink = 1 mA
Isource = 1 mA
R_RES
Pull up Resistor
V_OL
Output level logic low
Isource = 2 mA
SLVSC09A – MAY 2013 – REVISED JUNE 2013
MIN TYP
MAX UNITS
0.7 × VCC
50
0.9 × VCC
2
V
0.3 × VCC V
100
150 kΩ
V
0.1 × VCC V
3
4 kΩ
0.1 × VCC V
VB
Enable
VIH
VIL
VCC
VDD
Band Gap
Charge Pump
Sleep
Device Active
Sleep
Figure 27. ENABLE Timing Chart
Table 13. Recommended Pin Termination
PIN NAME
TEST
DESCRIPTION
Test mode input
TERMINATION
OPEN
Fault Detection
ITEMS
VB - Overvoltage
VB - Undervoltage
CP - Overvoltage
CP - Undervoltage
VCC - Overvoltage
VCC - Under Voltage
VCC - Overcurrent
Motor - Overcurrent
VDD - Overvoltage
VDD - Undervoltage
Thermal shutdown
Watch Dog
Clock Monitor
SPI FLTFLG
VBOV
VBUV
CPOV
CPUV
VCCOV
-
VCCOC
MTOC
VDDOV
-
TSD
-
-
Table 14. Fault Detection
Pre Driver⁽¹⁾
FAULT ⁽²⁾
Disable
L
Disable
L
Disable
L
Disable
L
Disable
L
Disable ⁽³⁾
H
Disable
L
Disable
L
Disable
L
Disable ⁽³⁾
H
Disable
L
-
H
-
H
RES
H
H
H
H
H
L
H
H
H
L
H
L
L
Others
(1) Pre-driver is disabled if the conditions occur and SDNEN register bits are 1.
(2) FAULT pin is asserted to low if the conditions occur and FLTEN register bits are 1.
(3) Pre-driver is disabled by VCC undervoltage and VDD undervoltage conditions regardless of SPI register setting.
Copyright © 2013, Texas Instruments Incorporated
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