DRV3203-Q1_15 Datasheet, PDF (11/37 Pages) Texas Instruments – Three-Phase Brushless Motor Driver

DRV3203-Q1
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FLTCFG (address 0x02): Fault Detection Configuration Register
SLVSC09A – MAY 2013 – REVISED JUNE 2013
Bit Name
Type Reset Description
7
FLGLATCH_EN RW 0
Fault-flag (FLTFLG*) latch enable
0: Fault events do not latch fault-flag register bits.
1: Latching of fault-flag register bits by the fault events occurs. The flag bits remain asserted until
cleared.
6:4 MTOCTH
RW 000 Motor overcurrent detection threshold
000: 1.32 V
001: 1.65 V
010: 1.98 V
011: 2.31 V
100: 2.64 V
Others: 1.32 V
3
RSVD
R
0
Reserved
2
VCCUVTH
RW 0
VCC undervoltage detection threshold
0: 2.3 V
1: 2.4 V
1:0 VBUVTH
RW 00
VB undervoltage detection threshold
00: 4 V
01: 4.5 V
10: 5 V
11: 5.5 V
FLTEN0 (address 0x04): FAULT Pin Enable Register 0
Bit Name
7
FE_MTOC
6
FE_VCCOC
5
FE_VCCOV
4
FE_VDDOV
3
FE_CPOV
2
FE_CPUV
1
FE_VBOV
0
FE_VBUV
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
1
1
1
1
1
1
1
1
Description
FAULT pin enable of FLTFLG0 register bits.
0: Assertion of the FAULT pin does not occur when the fault flag bit is 1
1: Assertion of the FAULT pin to low level occurs when the fault flag bit is 1. See Figure 6
FLTEN1 (address 0x05): FAULT Pin Enable Register 1
Bit Name
7:1 RSVD
0
FE_TSD
Type
R
RW
Reset Description
0000 000 Reserved
1
FAULT pin enable of TSD flag bit
0: Assertion of the FAULT pin does not occur when the fault flag bit is 1
1: Assertion of the FAULT pin to low level occurs when the TSD flag bit is 1. See Figure 6
Copyright © 2013, Texas Instruments Incorporated
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