THS0842 Datasheet, PDF (3/29 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
ADC pipeline block diagram
SHA
ADC
+
–
SHA
DAC
SHA
SHA
SHA
SHA
ADC
2
2
2
2
2
2
2
Correction Logic
Output Buffers
D0(LSB)–D7(MSB)
The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. Digital correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic ensures no missing codes over the full operating temperature range.
circuit diagrams of inputs and outputs
ALL DIGITAL INPUT CIRCUITS
DVDD
AIN INPUT CIRCUIT
AVDD
REFERENCE INPUT CIRCUIT
AVDD
Internal
Reference
Generator
REFTO
or
REFBO
0.5 pF
D0–D7 OUTPUT CIRCUIT
DRVDD
D
AVDD
OE
REFBI
or
REFTI
D_Out
DRVSS
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