THS0842 Datasheet, PDF (17/29 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
PRINCIPLES OF OPERATION
definitions of specifications and terminology
integral nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two endpoints.
differential nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
Therefore this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined
here as the step size for the device under test, i.e. (last transition level – first transition level)/(2n –2). Using this
definition for DNL separates the effects of gain and offset error. A minimum DNL better than –1 LSB ensures
no missing codes.
offset and gain error
Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage
– that will switch the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the
voltage corresponding to 1/2 LSB to the bottom reference level. The voltage corresponding to 1 LSB is found
from the difference of top and bottom references divided by the number of ADC output levels (256).
Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage
– that will switch the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting
the voltage corresponding to 1.5 LSB from the top reference level. The voltage corresponding to 1 LSB is found
from the difference of top and bottom references divided by the number of ADC output levels (256).
analog input bandwidth
The analog input bandwidth is defined as the maximum frequency of a 1-dBFS input sine wave that can be
applied to the device for which an extra 3-dB attenuation is observed in the reconstructed output signal.
output timing
Output timing t_d(o) is measured from the 1.5-V level of the CLK input falling edge to the 10%/90% level of the
digital output. The digital output load is not higher than 10 pF.
Output hold time t_h(o) is measured from the 1.5-V level of the CLK input falling edge to the10%/90% level of the
digital output. The digital output load is not less than 2 pF.
Aperture delay t_d(A) is measured from the 1.5-V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing t_dis is measured from the V_IH(min) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OE timing t_en is measured from the V_IL(max) level of OE to the instant when the output data reaches V_OH(min)
or V_OL(max) output levels. The digital output load is not higher than 10 pF.
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