THS0842 Datasheet, PDF (27/29 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
PRINCIPLES OF OPERATION
THS0842
SN74LVC827A
DA7
1D7
1Q7
8
8
DA0
1D0
1Q0
1D8
1Q8
1D9
1Q9
COUT
COUT
SN74LVC374A
1D7
1Q7
1D0
1Q0
CLK
FIFO
1D15
1D8
1Q15
16
1D7 1Q0
TMS320 DSP
1D0
HF Flag
WRTCLK
INTR
Figure 27. Single Bus FIFO Connection to DSP Example
THS0842
8
DA7– DA0
FIFO
D7 – D0
16
1Q15 – 1Q0
DSP
8
DB7– DB0
COUT
D16 – D9
> WRTCLK
HF Flag
INTR
Figure 28. Dual Bus FIFO Connection to DSP Example
layout, decoupling and grounding rules
Proper grounding and layout of the PCB on which the THS0842 is populated are essential to achieve the stated
performance. It is advisable to use separate analog and digital ground planes that are spliced underneath the
device. The THS0842 has digital and analog terminals on opposite sides of the package to make this easier.
Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB.
It is advisable to do this at one point in close proximity to the THS0842.
As for power supplies, separate analog and digital supply terminals are provided on the device (AV_DD/DV_DD).
The supply to the digital output drivers is kept separate also (DRV_DD). Lowering the voltage on this supply to
3 V instead of the nominal 3.3 V improves performance because of the lower switching noise caused by the
output buffers.
Because of the high sampling rate and switched-capacitor architecture, THS0842 generates transients on the
supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic
of the THS0842 EVM is recommended.
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