THS0842 Datasheet, PDF (18/29 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246 – DECEMBER 1999
PRINCIPLES OF OPERATION
definitions of specifications and terminology (continued)
pipeline delay (latency)
The number of clock cycles between conversion initiation on an input sample and the corresponding output data
being made available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided
on every clock cycle. In order to know when data is stable on the output pins, the output delay time t_d(o) (i.e.,
the delay time through the digital output buffers) needs to be added to the pipeline latency. Note that since the
max t_d(o) is more than 1/2 clock period at 80 MHz, data cannot be reliably clocked in on a rising edge of CLK
at this speed. The falling edge should be used.
The THS0842 implements a high-speed 40 MSPS converter in a cost effective CMOS process. Powered from
3.3 V, the single pipeline design architecture ensures low power operation and 8-bit accuracy. Signal inputs are
differential and the clock signal is single ended. The digital inputs are 3.3 V TTL/CMOS compatible. Internal
voltage references are included for both bottom and top voltages. Therefore, the converter forms a
self-contained solution. Alternatively, the user may apply externally generated reference voltages. In doing so,
both input offset and input range can be modified to suit the application.
The analog input signal is captured by a high speed sampling and hold. Multiple stages will generate the output
code with a pipeline delay of 6.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit
output word. All digital logic operates at the rising edge of CLK.
analog input
THS0842
RS
RSW
RS
RSW
VS+
VS–
CI
CI
+
–
VCM
+
–
VCM
Figure 18. Simplified Equivalent Input Circuit
A first-order approximation for the equivalent analog input circuit of the THS0842 is shown in Figure 18. The
equivalent input capacitance C_I is 5 pF typical. The input must charge/discharge this capacitance within the
sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides
the charging current through the switch resistance R_SW (200 Ω) of S1 and quickly settles. In this case the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on C_I, the hold
capacitor requires no input current and the equivalent input impedance is very high.
18
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