BQ24640 Datasheet, PDF (3/25 Pages) Texas Instruments – High-Efficiency Synchronous Switch-Mode Super Capacitor Charger

bq24640
www.ti.com
SLUSA44 – MARCH 2010
PIN
NO. NAME
14 PH
15 HIDRV
16 BTST
PowerPad
PIN FUNCTIONS (continued)
TYPE ⁽¹⁾
PIN DESCRIPTION
P Switching node, charge current output inductor connection. Connect the 0.1-mF bootstrap capacitor from PH
to BTST.
O PWM high side driver output. Connect to the gate of the high side N-channel power MOSFET with a short
trace.
P PWM high side driver positive supply. Connect the 0.1-mF bootstrap capacitor from PH to BTST.
Exposed pad beneath the IC. Always solder Power Pad to the board, and have vias on the Power Pad plane
star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to
dissipate the heat.
PART NUMBER
bq24640
IC MARKING
OGA
ORDERING INFORMATION
PACKAGE
ODERING NUMBER
(Tape and Reel)
16-PIN 3.5×3.5 mm QFN
bq24640RVAR
bq24640RVAT
QUANTITY
3000
250
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
bq24640
(RVA)
UNITS
q_JA
q_JC(top)
q_JB
y_JT
y_JB
q_JC(bottom)
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance ⁽³⁾
Junction-to-board thermal resistance ⁽⁴⁾
Junction-to-top characterization parameter ⁽⁵⁾
Junction-to-board characterization parameter ⁽⁶⁾
Junction-to-case(bottom) thermal resistance ⁽⁷⁾
(QFN-16) PINS
43.8
81
16
0.6
15.77
4
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y_JB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2010, Texas Instruments Incorporated
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