BQ24640 Datasheet, PDF (19/25 Pages) Texas Instruments – High-Efficiency Synchronous Switch-Mode Super Capacitor Charger

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SLUSA44 – MARCH 2010
FOM_top = R_DS(on) ´ Q_GD; FOM_bottom = R_DS(on) ´ Q_G
(11)
The lower the FOM value, the lower the total power loss. Usually lower R_DS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle
(D=V_OUT/V_IN), charging current (I_CHG), MOSFET's on-resistance R_DS(ON)), input voltage (V_IN), switching frequency
(F), turn on time (t_on) and turn off time (t_off):
P_top = D ´ I_CHG2
´ R_DS(on) +
1
2
´ V_IN
´ I_CHG
´ (t_on + t_off ) ´ f_S
(12)
The first item represents the conduction loss. Usually MOSFET R_DS(ON) increases by 50% with 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are
given by:
t_on
=
Q_{SW ,}
I_on
t_off
=
Q_SW
I_off
(13)
where Q_SW is the switching charge, Ion is the turn-on gate driving current and IOFF is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(Q_GD) and gate-to-source charge (Q_GS):
1
Q_SW = Q_GD + ₂ ´ Q_GS
(14)
Gate driving current total can be estimated by REGN voltage (V_REGN), MOSFET plateau voltage (V_PLT), total
turn-on gate resistance (R_ON) and turn-off gate resistance R_OFF) of the gate driver:
I_on
=
V_REGN - V_{plt ,}
R _on
I_off
=
V_plt
R _off
(15)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
P_bottom = (1 - D) ´ I_CHG ² ´ R_DS(on)
(16)
If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum
charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10mΩ charging current sensing
resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body
diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate driver power loss contributes to the dominant losses on controller IC, when the buck converter is
switching. Choosing the MOSFET with a small Q_{g_total} will reduce the IC power loss to avoid thermal shutdown.
P_{ICLoss_driver} = V_IN ´ Q_{g_total} ´ f_S
(17)
Where Q_{g_total} is the total gate charge for both upper and lower MOSFET at 6V VREGN.
INPUT FILTER DESIGN
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin may be beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
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