BQ24640 Datasheet, PDF (13/25 Pages) Texas Instruments – High-Efficiency Synchronous Switch-Mode Super Capacitor Charger

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SLUSA44 – MARCH 2010
• Thermal Shut (TSHUT) is not valid
• TS fault is not detected
One of the following conditions will stop on-going charging:
• CE is LOW;
• Adapter is removed, causing the device to enter VCCLOWV;
• The device is in SLEEP mode (i.e., VCC < SRN);
• Adapter is over voltage;
• The REGN or VREF LDOs voltage are not valid;
• TSHUT IC temperature threshold is reached;
• TS voltage goes out of range indicating the temperature is too hot or too cold.
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current to ensure there is no overshoot or stress on
the output capacitor. The soft-start consists of stepping-up the charge regulation current into 8 evenly divided
steps up to the programmed charge current. Each step lasts around 1.6ms, for a typical rise time of 13ms. No
external components are needed for this function.
CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter is selected to give a resonant frequency of 12 kHz–17 kHz, where resonant
frequency, f_o, is given by:
1
¦_o =
2p L_oC_o
(3)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset in order to allow zero percent duty-cycle when the EAO signal is below the
ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle
PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper
device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2V for more
than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power
MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver
returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage
current discharging the BTST capacitor below the 4.2 V, and the reset pulse is issued.
The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
output voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.
SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5A inductor current for
a 10mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is
break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where
both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the
low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. During
synchronous mode the inductor current is always flowing and converter operates in continuous conduction mode
(CCM), creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5A inductor
current on 10mΩ sense resistor). The charger is forced into non-synchronous mode when the average SRP-SRN
voltage is lower than 1.25mV (125mA on 10mΩ sense resistor).
Copyright © 2010, Texas Instruments Incorporated
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