DRV8880_15 Datasheet, PDF (29/48 Pages) Texas Instruments – DRV8880 2-A Stepper Motor Driver With AutoTune™

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DRV8880
SLVSD18A – JUNE 2015 – REVISED JULY 2015
7.3.11 Protection Circuits
The DRV8880 is fully protected against undervoltage, charge pump undervoltage, overcurrent, and
overtemperature events.
7.3.12 VM UVLO (UVLO2)
If at any time the voltage on the VM pin falls below the VM undervoltage lockout threshold voltage (V_UVLO2), all
FETs in the H-bridge will be disabled, the charge pump will be disabled, and the nFAULT pin will be driven low.
Operation will resume when VM rises above the UVLO2 threshold. The nFAULT pin will be released after
operation has resumed.
The indexer position is not reset by this fault even though the output drivers are disabled. The indexer position is
maintained and internal logic remains active until VM falls below the logic undervoltage threshold (V_UVLO1).
7.3.13 Logic Undervoltage (UVLO1)
If at any time the voltage on the VM pin falls below the logic undervoltage threshold voltage (V_UVLO1), the internal
logic is reset, and the V3P3 regulator is disabled. Operation will resume when VM rises above the UVLO1
threshold. The nFAULT pin is logic low during this state since it is pulled low upon encountering VM
undervoltage. Decreasing VM below this undervoltage threshold will reset the indexer position.
7.3.14 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the charge pump undervoltage lockout threshold voltage, all
FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Operation will resume when VCP
rises above the CPUV threshold. The nFAULT pin will be released after operation has resumed.
7.3.15 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume. The nFAULT
pin will be released after operation has resumed.
7.3.16 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than t_OCP, all FETs in the H-bridge will be disabled and nFAULT will be
driven low. In addition to this FET current limit, an overcurrent condition is also detected if the voltage at xISEN
exceeds V_OCP.
The overcurrent fault response can be set to either latched mode or retry mode:
V3P3
V3P3
ENABLE
FAULTn
5.1 kŸ
Device
Logic
ENABLE
FAULTn
Short
Detect
Device
Logic
Figure 25. Latched OCP Mode
Figure 26. Retry OCP Mode
In latched mode, operation will resume after the ENABLE pin is brought logic low for at least 1 μs to reset the
output driver. The nFAULT pin will be released after ENABLE is returned logic high. Removing and re-applying
VM or toggling nSLEEP will also reset the latched fault.
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