PCI1450 Datasheet, PDF (26/132 Pages) Texas Instruments – PC Card Controllers

PCI1450 GFN/GJG
PC CARD CONTROLLER
SCPS044 – SEPTEMBER 1998
SDA
SCL
Start
Condition
Stop
Condition
Data Line Stable,
Data Valid
Change of
Data Allowed
Figure 6. Serial EEPROM Start/Stop Conditions and BIt Transfers
Each address byte and data transfer is followed by an acknowledge bit, as indicated in Figure 5. When the
PCI1450 transmits the addresses, it returns the SDA signal to the high state and 3-states the line. The PCI1450
then generates an SCL clock cycle and expects the EEPROM to pull down the SDA line during the acknowledge
pulse. This procedure is referred to as a slave acknowledge with the PCI1450 transmitter and the EEPROM
receiver. Figure 7 illustrates general acknowledges.
During the data byte transfers from the serial EEPROM to the PCI1450, the EEPROM clocks the SCL signal.
After the EEPROM transmits the data to the PCI1450, it returns the SDA signal to the high state and 3-states
the line. The EEPROM then generates an SCL clock cycle and expects the PCI1450 to pull down the SDA line
during the acknowledge pulse. This procedure is referred to as a master acknowledge with the EEPROM
transmitter and the PCI1450 receiver. Figure 7 illustrates general acknowledges.
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 7. Serial EEPROM Protocol – Acknowledge
EEPROM interface status information is communicated through the general status register located at PCI offset
85h. The EEDETECT bit in this register indicates whether or not the PCI1450 serial EEPROM circuitry detects
the pulldown resistor on LATCH. An error condition, such as a missing acknowledge, results in the DATAERR
bit being set. The EEBUSY bit is set while the subsystem ID register is loading (serial EEPROM interface is
busy).
PC Card applications overview
This section describes the PC Card interfaces of the PCI1450. A discussion is provided on PC Card recognition,
which details the card interrogation procedure. The card powering procedure is discussed in this section
including the protocol of the P2C power switch interface. The internal ZV buffering provided by the PCI1450
and programming model is detailed in this section. Also, standard PC Card register models are described, as
well as a brief discussion of the PC Card software protocol layers.
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