PCI1450 Datasheet, PDF (107/132 Pages) Texas Instruments – PC Card Controllers

PCI1450 GFN/GJG
PC CARD CONTROLLER
SCPS044 – SEPTEMBER 1998
socket event register
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Socket event
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3† 2† 1† 0†
Name
Socket event
Type
R
R
R
R
R
R
R
R
R
R
R
R R/WC R/WC R/WC R/WC
Default 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register: Socket event
Type:
Read-only, Read/Write to Clear
Offset:
CardBus Socket Address + 00h
Default: 0000 0000h
Description: This register indicates a change in socket status has occurred. These bits do not indicate what
the change is, only that one has occurred. Software must read the socket present state
register for current status. Each bit in this register can be cleared by writing a 1 to that bit. The
bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in
the socket force event register. All bits in this register are cleared by PCI reset. They may be
immediately set again, if, when coming out of PC Card reset, the bridge finds the status
unchanged (i.e., CSTSCHG reasserted or card detect is still true). Software needs to clear
this register before enabling interrupts. If it is not cleared and interrupts are enabled, then an
interrupt is generated based on any bit set and not masked.
Table 62. Socket Event Register Description
BIT
31–4
3†
TYPE
R
R/WC
FUNCTION
Reserved. These bits return 0s when read.
PWREVENT. Power cycle. This bit is set when the PCI1450 detects that the PWRCYCLE bit in the socket present state
register has changed. This bit is cleared by writing a 1.
2†
R/WC
CD2EVENT. CCD2. This bit is set when the PCI1450 detects that the CDETECT2 field in the socket present state register
has changed. This bit is cleared by writing a 1.
1†
R/WC
CD1EVENT. CCD1. This bit is set when the PCI1450 detects that the CDETECT1 field in the socket present state register
has changed. This bit is cleared by writing a 1.
CSTSEVENT. CSTSCHG. This bit is set when the CARDSTS field in the socket present state register has changed state.
0†
R/WC For CardBus cards, this bit is set on the rising edge of the CSTSCHG signal. For 16-bit PC Cards, this bit is set on both
transitions of the CSTSCHG signal. This bit is reset by writing a 1.
† _{This bit is cleared only by the assertion of G_RST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST}
or G_RST.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
107