PCI1450 Datasheet, PDF (114/132 Pages) Texas Instruments – PC Card Controllers

PCI1450 GFN/GJG
PC CARD CONTROLLER
SCPS044 – SEPTEMBER 1998
distributed DMA (DDMA) registers
The DMA base address, programmable in PCI configuration space at offset 98h, points to a 16-byte region in
PCI I/O space where the DDMA registers reside. Table 68 summarizes the names and locations of these
registers. These registers are identical in function, but different in location from the Intel 8237 DMA controller.
The similarity between the register models retains some level of compatibility with legacy DMA and simplifies
the translation required by the master DMA device when forwarding legacy DMA writes to DMA channels.
These PCI1450 DMA register definitions are identical to those registers of the same name in the 8237 DMA
controller; however, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment.
In such cases, the PCI1450 will implement these obsolete register bits as nonfunctional, read-only bits. The
reserved registers shown in Table 68 are implemented as read-only, and return 0s when read. Writes to
reserved registers have no effect.
TYPE
R
Reserved
W
R
Reserved
W
R
N/A
W
Mode
R
Multichannel
W
Mask
Table 68. Distributed DMA Registers
Page
Reserved
Reserved
Reserved
REGISTER NAME
N/A
Request
N/A
Master clear
Current address
Base address
Current count
Base count
Status
Command
Reserved
DMA BASE
ADDRESS
OFFSET
00h
04h
08h
0Ch
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