DAC8803 Datasheet, PDF (26/30 Pages) Texas Instruments – Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter

DAC8803
SBAS340A – JANUARY 2005 – REVISED APRIL 2005
www.ti.com
PCB LAYOUT
In printed circuit board (PCB) layout, all analog ground, A_GNDX, should be tied together. Amplifiers suitable for:
Table 1. Control Logic Truth Table⁽¹⁾
CS CLK LDAC RS MSB
SERIAL SHIFT REGISTER
H
X
H
H
X No effect
L
L
H
H
X No effect
L
↑+
H
H
X Shift register data advanced one bit
L
H
H
H
X No effect
↑+
L
H
H
X No effect
H
X
H
X
H
X
H
X
X
↑+
L
H
H
H
↑+
H
H
L
H
L
X No effect
X No effect
X No effect
0 No effect
H No effect
INPUT REGISTER
Latched
Latched
Latched
Latched
Selected DAC updated with current SR
contents
Latched
Latched
Latched
Latched data = 0000h
Latched data = 8000h
DAC REGISTER
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Latched
Latched data = 0000h
Latched data = 8000h
(1) ↑+ Positive logic transition; X = Do not care
Table 2. Serial Input Register Data Format, Data Loaded MSB First⁽¹⁾
Bit B17 B16 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3 B2 B1 B0
(MSB)
(LSB)
Data A1
A0
X
X D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3 D2 D1 D0
(1) Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line's positive edge returns to
logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8803 shift register are ignored, only the
last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 3. Address Decode
A1
A0
DAC DECODE
0
0
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D
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