DAC8803 Datasheet, PDF (24/30 Pages) Texas Instruments – Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter

DAC8803
SBAS340A – JANUARY 2005 – REVISED APRIL 2005
CS
CLK
SDI
SDO
EN
D0
16
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
ADC _A
B
C
D
2:4
Decode
Input
Register R
V_REF A B C D
DAC A
Register R
DAC A
www.ti.com
V_DD
R_FBA
I_OUTA
A_GNDA
Input
Register R
DAC B
Register R
DAC B
R_FBB
I_OUTC
A_GNDB
Input
Register R
DAC C
Register R
DAC C
R_FBC
I_OUTC
A_GNDC
Power-
on
Reset
Input
Register R
Set MSB
DAC D
Register R
Set
MSB
DAC D
R_FBD
I_OUTD
A_GNDD
A_GNDF
DGND
MSB
LDAC
RS
V_SS
Figure 56. System Level Digital Interfacing
SERIAL DATA INTERFACE
The DAC8803 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of the DAC8803 is
clocked into the serial input register in an 14-bit data-word format. MSB bits are loaded first. Table 3 defines the
16 data-word bits for the DAC8803.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked
in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register
are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the
DAC8803. Keeping the CS line low between the first, second, and third byte transfers results in a successful
serial register update. Similarly, two right-justified data bytes can be written to the DAC8803. Keeping the CS line
low between the first and second byte transfer will result in a successful serial register update.
24