DAC8803 Datasheet, PDF (25/30 Pages) Texas Instruments – Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter

DAC8803
www.ti.com
SBAS340A – JANUARY 2005 – REVISED APRIL 2005
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For DAC8803, Table 1,
Table 3 and Figure 57 define the characteristics of the software serial interface. Figures 8 and 9 show the
equivalent logic interface for the key digital control pins for DAC8803.
To Input Register
A
CS
Address
B
Decoder
C
D
CLK
EN
Shift Register
SDI
SDO
19^th/17^th
CLOCK
Figure 57. DAC8803 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
POWER ON RESET
When the V_DD power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The V_DD power supply should have a smooth
positive ramp without drooping in order to have consistent results, especially in the region of V_DD = 1.5 V to 2.3
V. The V_SS supply has no effect on the power-on reset performance. The DAC register data stays at zero or
half-scale setting until a valid serial register data load takes place.
ESD Protection Circuits
All logic-input pins contain back-biased ESD protection Zener diodes connected to ground (DGND) and V_DD as
shown in Figure 58.
V_DD
DIGITAL
INPUTS
5 kW
DGND
Figure 58. Equivalent ESD Protection Circuits
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