DS92LV3242TVSX Datasheet, PDF (24/31 Pages) Texas Instruments – DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
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– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500 Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual (literature number SNLA187), which is
available in PDF format from the TI LVDS & CML Solutions web site.
Typical Performance Characteristics
The waveforms below illustrate the typical performance of the DS92LV3241. The SER was given a PCLK and configured as
described below each picture. In all of the pictures the SER was configured with BISTEN pin set to logic HIGH. Each
waveform was taken by using a high impedance low capacitance differential probe to probe across a 100 ohm differential
termination resistor within one inch of TxOUT0+/-.
Figure 22. Serial Output Quad Mode, 85 MHz, VSEL = H, No
Pre-Emphasis
Figure 23. Serial Output Quad Mode, 85 MHz, VSEL = L, No
Pre-Emphasis
Figure 24. Serial Output Dual Mode, 50 MHz, VSEL = H, No
Pre-Emphasis
Figure 25. Serial Output Dual Mode, 50 MHz, VSEL = L, No
Pre-Emphasis
24
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