DS92LV3242TVSX Datasheet, PDF (11/31 Pages) Texas Instruments – DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
www.ti.com
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_ROCP
Receiver Output Clock Period
t_ROCP = t_CIP
(Dual Mode)
20
Figure 11
t_ROCP = t_CIP
(Quad Mode)
11.76
t_RODC
RxCLKOUT Duty Cycle
45
t_ROTR
t_ROTF
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
C_L = 8pF (lumped load)
(Dual Mode)
Figure 10
t_ROTR
LVCMOS Low-to-High Transition
Time
C_L = 8pF (lumped load)
(Quad Mode)
t_ROTF
LVCMOS High-to-Low Transition
Time
t_ROSC
RxOUT[31:0] Setup to RxCLKOUT
f = 50 MHz
(Dual Mode)
5.6
t_ROHC
RxOUT[31:0] Hold to RxCLKOUT
7.4
t_ROSC
RxOUT[31:0] Setup to RxCLKOUT
f = 85 MHz
(Quad Mode)
3.4
t_ROHC
RxOUT[31:0] Hold to RxCLKOUT
3.4
t_HZR
Data Output High to TRI-STATE
Figure 13
Delay
t_LZR
Data Output Low to TRI-STATE
Delay
t_ZHR
Data Output TRI-STATE to High
Delay
t_ZLR
Data Output TRI-STATE to Low
Delay
t_RD
Deserializer Propagation Delay –
f = 20 MHz
Latency
(Dual Mode)
Figure 12
f = 50 MHz
(Dual Mode)
f = 40 MHz
(Quad Mode)
f = 85 MHz
(Quad Mode)
t_RPLLS ⁽¹⁾
TOL_JIT
t_LVSKR
Deserializer PLL Lock Time
Deserializer Input Jitter Tolerance
LVDS Differential Input Skew
Tolerance
20 MHz – 50 MHz
(Dual Mode)
Figure 13
40 MHz – 85 MHz
(Quad Mode)
Figure 13
20 MHz – 85 MHz
Figure 17
(1) t_RPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode.
Typ
t_ROCP
t_ROCP
50
3.2
3.5
2.4
1.9
0.5 x
t_ROCP
0.5 x
t_ROCP
0.5 x
t_ROCP
0.5 x
t_ROCP
5
5
5
5
5.5 x
t_ROCP +
3.35
5.5 x
t_ROCP +
6.00
12.0 x
t_ROCP +
7.4
12.0 x
t_ROCP +
5.7
0.25
Max
50
25
55
10
10
10
10
128k x
t_ROCP
256k x
t_ROCP
0.4 x
t_ROCP
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
ns
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