DS92LV3242TVSX Datasheet, PDF (19/31 Pages) Texas Instruments – DS92LV3241/DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
www.ti.com
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
AT-SPEED BIST FEATURE
The DS92LV3241/ DS92LV3242 serial link is equipped with built-in self-test (BIST) capability to support both
system manufacturing and field diagnostics. BIST mode is intended to check the entire high-speed serial
interface at full link-speed without the use of specialized and expensive test equipment. This feature provides a
simple method for a system host to perform diagnostic testing of both SER and DES. The BIST function is easily
configured through the SER BISTEN pin. When the BIST mode is activated, the SER generates a PRBS
(pseudo-random bit sequence) pattern (2^7-1). This pattern traverses each lane to the DES input. The
DS92LV3242 includes an on-chip PRBS pattern verification circuit that checks the data pattern for bit errors and
reports any errors on the data output pins of the DES.
The AT-Speed BIST feature is enabled by setting the BISTEN to High on SER. The BISTEN input must be High
or Low for 4 or more TxCLKIN clock cycles in order to activate or deactivate the BIST mode. An input clock
signal for the Serializer TxCLKIN must also be applied during the entire BIST operation. Once BIST is enabled,
all the Serializer data inputs (TxIN[31:0]) are ignored and the DES outputs (RxOUT[31:0]) are not available. Next,
the internal test pattern generator for each channel starts transmission of the BIST pattern from SER to DES.
The DES BIST mode will be automatically activated by this sequence. A maximum of 128 consecutives clock
symbols on DS92LV3242 DES is needed to detect BIST enable function. The BIST is implemented with
independent transmit and receive paths for the four serial links. Each channel on the DES will be individually
compared against the expected bit sequence of the BIST pattern.
TxCLKIN
PDB (High)
BISTEN
2.0V
0.8V
BIST disabled
BIST enabled
BIST disabled
4 x tCIP
4 x tCIP
Figure 18. BIST Test Enabled/Disabled
Under the BIST mode, the DES parallel outputs on RxOUT[31:0] are multiplexed to represent BIST status
indicators. The pass/fail status of the BIST is represented by a Pass flag along with an Error counter. The Pass
flag output is designated on DES RxOUT0 for Channel 0, and RxOUT8 for Channel 1. The DES's PLL must first
be locked to ensure the Pass status is valid. The output Pass status pin will stay LOW and then transition to High
once 44*10^6 symbols are achieved across each of the respective transmission links. The total time duration of
the test is defined by the following: 44*10^6 x tCIP . After the Pass output flags reach a HIGH state, it will not
drop to LOW even if subsequent bit errors occurred after the BIST duration period. Errors will be reported if the
input test pattern comparison does not match. If an error (miss-compare) occurs, the status bit is latched on
RxOUT[7:1] for Channel 0, and RxOUT[15:9] for Channel 1; reflecting the number of errors detected. Whenever
a data bit contains an error, the Error counter bit output for that corresponding channel goes HIGH. Each counter
for the serial link utilizes a 7-bit counter to store the number of errors detected (0 to 127 max).
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: DS92LV3241 DS92LV3242