DRV8711_15 Datasheet, PDF (24/44 Pages) Texas Instruments – DRV8711 Stepper Motor Controller IC

DRV8711
SLVSC40E – JUNE 2013 – REVISED MARCH 2015
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7.4 Device Functional Modes
7.4.1 RESET and SLEEPn Operation
An internal power-up reset circuit monitors the voltage applied to the VM pin. If VM falls below the VM
undervoltage lockout voltage, the part is reset, as described below for the case of asserting the RESET pin.
If the RESET pin is asserted, all internal logic including the indexer is reset. All registers are returned to their
initial default conditions. The power stage will be disabled, and all inputs, including STEP and the serial interface,
are ignored when RESET is active.
On exiting reset state, some time (approximately 1 mS) needs to pass before the part is fully functional.
Applying an active low input to the SLEEPn input pin will place the device into a low power state. In sleep mode,
the motor driver circuitry is disabled, the gate drive regulator and charge pump are disabled, and all analog
circuitry is placed into a low power state. The digital circuitry in the device still operates, so the device registers
can still be accessed via the serial interface.
When SLEEPn is active, the RESET pin does not function. SLEEPn must be exited before RESET will take
effect.
When exiting from sleep mode, some time (approximately 1 mS) needs to pass before applying a STEP input, to
allow the internal circuitry to stabilize.
7.4.2 Microstepping Drive Current
Figure 16 shows examples of stepper motor current in one of the windings. Because these waveforms are
dependent on DRV8711 register settings as well as the external FETs, sense resistor, and stepper motor, they
should only be used as a reference.
Figure 16. Microstepping Drive Current
7.5 Programming
7.5.1 Serial Data Format
The serial data consists of a 16-bit serial write, with a read/write bit, 3 address bits and 12 data bits. The 3
address bits identify one of the registers defined in the register section above. To complete the read or write
transaction, SCS must be set to a logic 0.
To write to a register, data is shifted in after the address as shown in the timing diagram below. The first bit at
the beginning of the access must be logic low for a write operation.
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