DRV8711_15 Datasheet, PDF (23/44 Pages) Texas Instruments – DRV8711 Stepper Motor Controller IC

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DRV8711
SLVSC40E – JUNE 2013 – REVISED MARCH 2015
7.3.10.2 External Stall Detection
To use an external microcontroller to manage stall detection, the EXSTALL bit in the CTRL register is set to 1. In
this mode, the STALLn / BEMFVn output pin is used to signal a valid back EMF measurement is ready. In
addition, the SDT and SDTLAT bits are also set at this time.
BEMFVn and BEMF are still valid outputs in this mode even if the step time is smaller than SMPLTH time.
When the BEMFVn pin goes active low, it is an indication that a valid back EMF voltage measurement is
available. This signal could be used, for example, to trigger an interrupt on a microcontroller. The microcontroller
can then sample the voltage present (using an A/D converter) on the BEMF pin.
After sampling the back EMF voltage, the microcontroller writes a 0 to the SDTLAT bit to clear the SDT bit and
BEMFVn pin, in preparation for the next back EMF sample. If the SDTLAT bit is not cleared by the
microcontroller, it will automatically be cleared in the next zero-current step.
For either internal or external stall detection, at very high motor speeds when the PWM duty cycle approaches
100%, the inductance of the motor and the short duration of each step may cause the time required for current
recirculation to exceed the step time. In this case, back EMF will not be correctly sampled, and stall detection
cannot function. This condition occurs most at high degrees of micro-stepping, because the zero current step
lasts for a shorter duration. It is advisable to run the motor at lower degrees of micro-stepping at higher speeds
to allow time for current recirculation if stall detection is needed in this condition.
7.3.11 Protection Circuits
The DRV8711 is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.11.1 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the voltage drop across the external FETs. If the voltage across a driven
FET exceeds the value programmed by the OCPTH bits in the DRIVE register for more than the time period
specified by the OCPDEG bits in the DRIVE register, an OCP event is recognized. When operating in direct
PWM mode, during an OCP event, the H-bridge experiencing the OCP event is disabled; if operating in indexer
mode, both H-bridges will be disabled. In addition, the corresponding xOCP bit in the STATUS register is set,
and the FAULTn pin is driven low. The H-bridge(s) will remain off, and the xOCP bit will remain set, until it is
written to 0, or the device is reset.
7.3.11.2 Predriver Fault
In PWM mode, if excessive current is detected on the gate drive outputs (which would be indicative of a
failed/shorted output FET or PCB fault), the H-bridge experiencing the fault is disabled, the xPDF bit in the
STATUS register is set, and the FAULTn pin is driven low. The H-bridge will remain off, and the xPDF bit will
remain set until it is written to 0 or the device is reset.
When in indexer mode, both H-bridges are disabled, the xPDF bit in the STATUS register is set, and the FAULTn
pin is driven low. The H-bridges will remain off, and the xPDF bit will remain set until it is written to 0 or the
device is reset.
7.3.11.3 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled, the OTS bit in the STATUS
register will be set, and the FAULTn pin will be driven low. Once the die temperature has fallen to a safe level
operation will automatically resume and the OTS bit will reset. The FAULTn pin will be released after operation
has resumed.
7.3.11.4 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all FETs in the H-
bridge will be disabled, the UVLO bit in the STATUS register will be set, and the FAULTn pin will be driven low.
Operation will resume and the UVLO bit will reset when VM rises above the UVLO threshold. The FAULTn pin
will be released after operation has resumed.
During any of these fault conditions, the STEP input pin will be ignored.
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