TL16C2552 Datasheet, PDF (23/34 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

TL16C2552
www.ti.com
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow Table 3.
Table 3. Summary of Accessible Registers
BIT
REGISTER ADDRESS
NO.
DLAB = 0
0
0
1
2
2
3
4
5
6
7
Receiver
Buffer
Register
(Read
Only)
Transmitte
r Holding
Register
(Write
Only)
Interrupt
Enable
Register
Interrupt
Ident
.Register
(Read
Only)
FIFO
Control
Register
(Write
Only)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
0
Data Bit Data Bit 0 Enable
0 if
FIFO
Word
Data
Data
Delta Clear
Bit 0
0 ⁽¹⁾
Received Interrupt
Enable
Length
Terminal
Ready
to Send
Data
Pending
Select Bit 0 Ready
(DR)
(∆CTS)
Available
(WLS0)
(DTR)
Interrupt
(ERBI)
1 Data Bit 1 Data Bit 1 Enable Interrupt ID Receiver
Word Request to Overrun Delta Data
Transmitter
Bit 1
FIFO
Length
Send
Error (OE) Set Ready
Holding
Reset Select Bit 1 (RTS)
(∆DSR)
Register
(WLS1)
Empty
Interrupt
(ETBEI)
Bit 1
2 Data Bit 2 Data Bit 2 Enable Interrupt ID Transmitter Number of OUT1 Parity Error Trailing
Receiver
Bit 2
FIFO
Stop Bits
(PE)
Edge Ring
Line Status
Reset
(STB)
Indicator
Interrupt
(TERI)
(ELSI)
Bit 2
3 Data Bit 3 Data Bit 3 Enable Interrupt ID DMA Mode Parity
INT
Framing Delta Data
Modem
Bit 3⁽²⁾
Select
Enable Enable, OP Error (FE) Carrier
Status
(PEN)
Control
Detect
Interrupt
(∆DCD)
(EDSSI)
Bit 3
4 Data Bit 4 Data Bit 4
0
0
Reserved Even Parity Loop
Break
Clear to
Bit 4
Select
Interrupt
Send
(EPS)
(BI)
(CTS)
5 Data Bit 5 Data Bit 5
0
0
Reserved Stick Parity Autoflow Transmitter Data Set
Bit 5
Control
Holding
Ready
Enable
Register
(DSR)
(AFE)
(THRE)
6 Data Bit 6 Data Bit 6
0
FIFOs
Receiver
Break
Enabled⁽²⁾ Trigger
Control
(LSB)
0
Transmitter Ring
Bit 6
Empty
Indicator
(TEMT)
(RI)
7 Data Bit 7 Data Bit 7
0
FIFOs
Receiver
Divisor
0
Enabled⁽²⁾ Trigger
Latch
(MSB) Access Bit
(DLAB)
Error in
RCVR
FIFO⁽²⁾
Data
Carrier
Detect
(DCD)
Bit 7
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.
0
Divisor
Latch
(LSB)
DLAB = 1
1
Divisor
Latch
(MSB)
2
Alternate
Function
Register
DLL
Bit 0
DLM
Bit 8
AFR
Concurrent
Write
Bit 1
Bit 9
BAUDOUT
Select
Bit 2
Bit 10
RXRDY
Select
Bit 3
Bit 11
0
Bit 4
Bit 12
0
Bit 5
Bit 13
0
Bit 6
Bit 14
0
Bit 7
Bit 15
0
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
• Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
• Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
• Bits 4 and 5: These two bits are reserved for future use.
• Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).
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