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TL16C2552 Datasheet, PDF (22/34 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
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TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
PRINCIPLES OF OPERATION
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Register Selection
DLAB (1)
A2
0
L
0
L
0
L
0
L
X
L
X
H
X
H
X
H
X
H
1
L
1
L
1
L
Table 1. Register Selection
A1
A0
REGISTER
L
L
Receiver buffer (read), transmitter holding register (write)
L
H
Interrupt enable register
H
L
Interrupt identification register (read only)
H
L
FIFO control register (write)
H
H
Line control register
L
L
Modem control register
L
H
Line status register
H
L
Modem status register
H
H
Scratch register
L
L
Divisor latch (LSB)
L
H
Divisor latch (MSB)
H
L
Alternate function register (AFR)
(1) The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this
bit location (see Table 4).
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
Line status register
Modem status register
TX
INT
Interrupt condition (receiver error flag)
Interrupt condition (received data available)
Interrupt condition (transmitter holding register
empty)
Interrupt condition (modem status changes)
OP
RTS
DTR
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
XMIT FIFO
Alternate function register (AFR)
Table 2. ACE Reset Functions
RESET CONTROL
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset MCR3
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
RESET STATE
All bits cleared (0 - 3 forced and 4 - 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits
4 - 5 are permanently cleared
All bits cleared
All bits cleared
All bits, except bit 3, cleared (6 - 7 permanent), MCR
3 set
Bits 5 and 6 are set; all other bits are cleared
Bits 0 - 3 are cleared; bits 4 - 7 are input signals
High
Output buffer enabled
Low
Low
Low
Read MSR/MR
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
MR/FCR1 - FCR0/DFCR0
MR/FCR2 - FCR0/DFCR0
Master reset
Low
Low
High
High
No effect
No effect
No effect
No effect
All bits cleared
All bits cleared
All bits cleared
22
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