TL16C2552 Datasheet, PDF (2/34 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
Each ACE is a speed and voltage range upgrade of
the TL16C550C, which in turn is a functional
upgrade of the TL16C450. Functionally equivalent to
the TL16C450 on power up or reset (single character
or TL16C450 mode), each ACE can be placed in an
alternate FIFO mode. This relieves the CPU of
excessive software overhead by buffering received
and to be transmitted characters. Each receiver and
transmitter store up to 16 bytes in their respective
FIFOs, with the receive FIFO including three
additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can
significantly reduce software overload and increase
system efficiency by automatically controlling serial
data flow using handshakes between the RTS output
and CTS input, thus eliminating overruns in the
receive FIFO.
Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem
and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial
conversions on data sent from its CPU after storing
the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each ACE includes complete modem control
capability and a processor interrupt system that can
be tailored to the application.
Each ACE includes a programmable baud rate
generator capable of dividing a reference clock with
divisors of from 1 to 65535, thus producing a 16×
internal reference clock for the transmitter and
receiver logic. Each ACE accommodates up to a
1.5-Mbaud serial data rate (24-MHz input clock). As
a reference point, that speed would generate a
667-ns bit time and a 6.7-µs character time (for 8,N,1
serial data), with the internal clock running at 24
MHz.
Each ACE has a TXRDY and RXRDY output that
can be used to interface to a DMA controller.
FN PACKAGE
(TOP VIEW)
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6 5 4 3 2 1 44 43 42 41 40
D5 7
D6 8
D7 9
A0 10
XTAL1 11
GND 12
XTAL2 13
A1 14
A2 15
CHSEL 16
INTB 17
TL16C2552FN
39 RXA
38 TXA
37 DTRA
36 RTSA
35 MFA
34 INTA
33 V_CC
32 TXRDYB
31 RIB
30 CDB
29 DSRB
18 19 20 21 22 23 24 25 26 27 28
RHB PACKAGE
(TOP VIEW)
D6 ¹
D7 ²
A0 ³
XTAL1 ⁴
XTAL2 ⁵
A1 ⁶
A2 ⁷
CHSEL ⁸
TL16C2552RHB
24 _RXA
23 _TXA
22 _RTSA
21 _INTA
20 _GND
19 _NC
18 _NC
17 _CTSB
NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA,
DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA, DTRB,
TXRDYA, TXRDYB outputs.
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