TIBPAL20L8-5C Datasheet, PDF (23/35 Pages) Texas Instruments – HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
HIGH-PERFORMANCE IMPACT-X ™ PAL^® CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
metastable characteristics of TIBPAL20R4-5C, TIBPAL20R6-5C, and TIBPAL20R8-5C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between V_IL and V_IH. This metastable condition
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and ∆t for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (∆t) after SCLK. The exclusive OR gate detects
the occurrence of a failure and increments the failure counter.
Data in
Noise
Generator
DUT
1D
SCLK
C1
VIH
Comparator
VIL
Comparator
1D
C1
1D
C1
1D
C1
MTBF
Counter
+
SCLK + ∆ t
Figure 9. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
Data
SCLK
SCLK + ∆ t
∆t
∆t
+ MTBF
Time (sec)
# Failures
trec = ∆ t – CLK to Q (max)
Figure 10. Timing Diagram
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