TIBPAL20L8-5C Datasheet, PDF (18/35 Pages) Texas Instruments – HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C
TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M
HIGH-PERFORMANCE IMPACT-X ™ PAL^® CIRCUITS
SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992
f_max SPECIFICATIONS
f_max without feedback, see Figure 3
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t_su + t_h).
However, the minimum fmax is determined by the minimum clock period (t_w high + t_w low).
+ _{) )} Thus, fmax without feedback
1
(twhigh
twlow) ^or (tsu ¹
th).
CLK
Logic
Array
C1
1D
tsu + th
or
tw high + tw low
Figure 3. f_max Without Feedback
f_max with internal feedback, see Figure 4
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
+ _{) * * Thus,} fmax with internal feedback
(tsu
1
tpd CLK to FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
C1
1D
tsu
tpd CLK - to - FB
Figure 4. f_max With Internal Feedback
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