XDM3730ACBP Datasheet, PDF (204/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
SPRS685D – AUGUST 2010 – REVISED JULY 2011
www.ti.com
Table 6-36. DSS Switching Characteristics—TFT Mode⁽⁴⁾ (continued)
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
DL2 t_{d(pclkA-acbiasA)} Delay time, output pixel clock dss_pclk active edge to –4.215 4.215 –4.658 4.658
ns
output data enable dss_acbias active level
DL3
DL4
DL5
t_d(pclkA-dV)
1 / t_c(pclk)
t_w(pclk)
Delay time, output pixel clock dss_pclk active edge to
output data dss_data[23:0] valid
Frequency⁽²⁾, output pixel clock dss_pclk
Pulse duration, output pixel clock dss_pclk low or high
–4.215
0.45P⁽¹⁾
4.215
74.3⁽³⁾
0.55P⁽¹⁾
(5)
–4.658
0.45P⁽¹⁾
4.658
66⁽³⁾
0.55P⁽¹⁾
(5)
ns
MHz
ns
(1) P = dss_pclk period in ns
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
(3) For the DSS (TFT mode) in HD-TV application, to run at full speed (74.3 MHz) it is recommended to use the dss_data[5:0] signals on
the dss_data[23:18] balls (H26, H25, E28, J26, AC27, AC28). In that case, the dss_data[23:18] signals are available on the sys_boot0,
sys_boot1, sys_boot3, sys_boot4, sys_boot5, and sys_boot6 balls (AH26, AG26, AF18, AF19, AE21, AF21) to run at full speed (74.3
MHz).
If the dss_data[5:0] signals are used on the dss_data[5:0] balls (AG22, AH22, AG23, AH23, AG24, AH24), OPP100 DSS (TFT mode)
are limited at 66 MHz. The values may change following the silicon characterization result.
(4) See Section 4.3.4, Processor Clocks.
(5) tW(pclk) = 0.66.P when DISPC_DIVISOR[6:0] PCD = 3.
DL4
DL5
dss_pclk
DL1
dss_vsync
DL0
dss_hsync
DL2
dss_acbias
DL3
dss_data[23:0]
SWPS038-055
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) The pixel clock frequency is programmable.
(3) All timings not illustrated in the waveform are progammable by software, and control signal polarity and driven edge of dss_pclk too.
(4) For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4).
Figure 6-30. DSS—TFT Mode
6.5.2.1.3 DSS—Parallel Interface—Bypass Mode—STN Mode
Table 6-38 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 6-31).
Table 6-37. DSS Timing Conditions—STN Mode
TIMING CONDITION PARAMETER
Output Condition
C_LOAD
Output load capacitance⁽¹⁾
VALUE
MIN
MAX
40
UNIT
pF
204 Timing Requirements and Switching Characteristics
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