XDM3730ACBP Datasheet, PDF (141/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
4.3.1 DPLL Characteristics
Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating
conditions.
Table 4-14. DPLL1 - DPLL2 - DPLL3 - DPLL5 Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
COMMENTS
vdda_dplls_dll
Supply voltage for DPLLs (MPU, IVA,
1.71
1.8
1.91
V
and Core) and DLL
vdda_dpll_per
Supply voltage for DPLL
(Peripherals)
1.71
1.8
1.91
V
f_input
f_internal
f_CLKINPHIF
f_CLKINPULOW
f_CLKOUT
f_CLKOUTx2
f_CLKOUTHIF
CLKINP Input frequency
Internal reference frequency
CLKINPHIF Input frequency
CLKINPULOW Input frequency
CLKOUT output frequency
CLKOUTx2 output frequency
CLKOUTHIF output frequency
0.032
0.032
10
0.001
10⁽¹⁾
20⁽¹⁾
10⁽³⁾
20⁽³⁾
52
52
1000
800
1000⁽²⁾
2000⁽²⁾
1000⁽⁴⁾
2000⁽⁴⁾
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FINP
REFCLK
FINPHIF
[M / (N + 1)] * FINP * [1 /
M2]
2 * [M / (N + 1)] * FINP * [1
/ M2]
FINPHIF / M3
2 * [M / (N + 1)] * FINP * [1
/ M3]
f_DCOCLKLDO
DCOCLKLDO output frequency
20
t_lock
Frequency lock time
2000
1.9 +
350*REFCLK
MHz 2 * [M / (N + 1)] * FINP
μs
p_lock
t_relock-L
p_relock-L
t_relock-F
p_relock-F
Phase lock time
Relock time—Frequency lock⁽⁵⁾ (Low
power bypass)
Relock time—Phase lock⁽⁵⁾ (Low
power bypass)
Relock time—Frequency lock⁽⁵⁾ (Fast
relock bypass)
Relock time—Phase lock⁽⁵⁾ (Fast
relock bypass)
1.9 +
μs
500*REFCLK
1.9 + 70*REFCLK μs DPLL in low-power mode:
lowcurrstdby = 1
1.9 +
120*REFCLK
μs DPLL in low-power mode:
lowcurrstdby = 1
0.05 +
70*REFCLK
μs DPLL in normal mode:
lowcurrstdby = 0
0.05 +
120*REFCLK
μs DPLL in normal mode:
lowcurrstdby = 0
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. For M2 > 1, the minimum frequency on these clocks will
further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
NAME
vdda_dpll_per
f_input
f_internal
f_CLKINPULOW
f_CLKOUT
f_DCOCLKLDO
t_lock
p_lock
t_relock-L
Table 4-15. DPLL4 Characteristics
DESCRIPTION
Supply voltage for DPLL (peripherals)
CLKINP input clock frequency
REFCLK internal reference frequency
CLKINPULOW bypass input
frequency
CLKOUT output clock frequency
MIN
1.71
0.5
0.5
0.001
10⁽¹⁾
TYP
1.8
MAX
1.91
60
2.5
800
2000⁽²⁾
Internal oscillator (DCO) output clock
500
frequency
Frequency lock time
Phase lock time
Relock time—Frequency lock⁽³⁾ (Low
power bypass)
2000
350*REFCLK
500*REFCLK
7.5 +
30*REFCLKs
UNIT
V
MHz
MHz
MHz
COMMENTS
FINP
REFCLK
MHz
MHz
[M / (N + 1)] * FINP * [1 /
M2]
[M / (N + 1)] * FINP
μs
μs
μs DPLL in low-power mode:
lowcurrstdby = 1
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Clock Specifications 141