XDM3730ACBP Datasheet, PDF (151/280 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
Table 5-1. DAC – Static Electrical Specifications⁽⁸⁾ (continued)
PARAMETER
CONDITIONS/ASSUMPTIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION
I_vdda-up
Analog Supply
Current⁽⁴⁾
DC mode No
Average current on vdda_dac, no
4.5
6.5
8.5
mA
load
load, 2 channels
AC mode No
load
Input code 50 (maximum output
voltage)
19
28
37
Full load 75-Ω
load
19
28
37
I_vdda-up (peak) Peak analog supply current
I_vdd-up
Digital supply current⁽⁵⁾
Lasts less than 1 ns
Average current, measured at f_CLK
= 54 MHz,
f_OUT = 2 MHz sine wave, vdd = 1.1
V
60
mA
2
mA
I_vdd-up (peak) Peak digital supply current⁽⁶⁾
Peak current, full-scale transition
8
mA
lasting less than 1 ns
I_vdda-down(9)
Analog supply current, total power
down⁽⁹⁾
T = 30ºC, vdda_dac = 1.8 V, no
load
12
μA
I_{vdda-stdby(9)}
Analog supply current, standby mode⁽⁹⁾ Bandgap and internal LDO are ON,
90
180
270
μA
all other analog blocks are OFF, no
load, T = 30 Cº
I_{vdd-down(pm)(9)} Digital supply current, total power
down⁽⁹⁾
T = 30ºC, Full Low-swing mode
or Partial Power
Management
High-swing mode
2
μA
6
I_{vdd-down(nopm)} Digital supply current, total power down T = 30ºC, VDD = 1.1 V, no Power
(no power management)
Management
60
μA
(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode). The INL at code 783 equals 0.
(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode). The INL at code 783 equals 0.
(3) Reference PSR measures the effect of a supply disturbance at cvideo1_out and cvideo2_out.
(4) The analog supply current I_vdda is directly proportional to the full-scale output current IFS and is insensitive to f_CLK.
(5) The digital supply current I_VDD is dependent on the digital input waveform, the DAC update rate f_CLK, and the digital supply VDD.
(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.
(7) See Section 5.6, Analog Supply (vdda_dac) Noise Requirements, for actual maximum ripple allowed on vdda_dac.
(8) For more information on code range definition, see Figure 5-4.
(9) For more information on AVDAC power-up, power-down, and standby mode configurations, see Display Subsystem / Display
Subsystem Functional Description / Video Encoder Functionalities / Video DAC Stage Power Management section of AM/DM37x
Technical Reference Manual (literature number SPRUGN4).
NOTE
High-swing mode is the default mode. The low-swing mode is not compliant with the NTSC
and PAL video-standards. It is used only for backwards compatibility to AM/DM37x.
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Video DAC Specifications 151