TLV320ADC3101_15 Datasheet, PDF (20/92 Pages) Texas Instruments – TLV320ADC3101 Low-Power Stereo ADC With Embedded miniDSPnull for Wireless Handsets and Portable Audio

TLV320ADC3101
SLAS553B – NOVEMBER 2008 – REVISED AUGUST 2015
Feature Description (continued)
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WORD
CLOCK
BIT
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
DATA
n-1 n-2 n-3
3 210
n-1 n-2 n-3
3 210
n-1 n-2 n-3
3
LD(n)
Ch_Offset_1 = 0
LD(n) = nth Sample of Left-Channel Data
RD (n)
Ch_Offset_1 = 0
RD(n) = nth Sample of Right-Channel Data
Figure 22. I²S Mode With Ch_Offset_1 = 0, Bit Clock Inverted
LD(n+1)
For I²S mode, the number of bit clocks per channel must be greater than or equal to the programmed word
length of the data. Also the programmed offset value must be less than the number of bit clocks per frame by at
least the programmed word length of the data.
10.3.6.4 DSP Mode
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and is
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 23 shows the standard timing for the DSP mode.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
n-1 n-2 n-3
3 2 1 0 ^{n-1 n-2 n-3}
3210
LD(n)
RD(n)
LD(n) = n'th sample of left channel date RD(n) = n'th sample of right channel date
Figure 23. DSP Mode (Standard Timing)
Figure 24 shows the DSP mode timing with Ch_Offset_1 = 1.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
n-1 n-2 n-3
3
LD (n+1)
DATA
n-1 n-2 n-3 3 2 1 0 n-1 n-2 n-3 3 2 1 0
LD(n)
Ch_Offset_1 = 1
LD(n) = nth Sample of Left-Channel DatA
RD(n)
RD(n) = nth Sample of Right-Channel Data
Figure 24. DSP Mode With Ch_Offset_1 = 1
Figure 25 shows the DSP mode timing with Ch_Offset_1 = 0 and bit clock inverted.
n-1 n-2 n-3
LD(n+1)
20
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