THS8083A Datasheet, PDF (20/64 Pages) Texas Instruments – TRIPLE 8 BIT 80 MSPS 3.3V VIDEO AND GRAPHICS

The PFD produces a digital error value, signaling the phase/frequency difference between the HS input and the
divided PLL output clock. The integrated digital PLL loop filter subsequently filters this error value. This filter consists
of proportional and integrator (accumulator) parts. Gains of both parts are programmable (GAIN_N and GAIN_P
register values), each with eight settings. The higher the programmed value, the higher the gain in either the
proportional or integrator portions of the filter, which translates into a wider capture range and faster acquisition but
also into higher steady-state jitter.
The PFD also provides a LOCK output on a dedicated terminal. This output has programmable hysteresis
(LD_THRES register value). Details are explained in the Register Description section. The LOCK output is made
available on a dedicated pin so that the user could implement additional functionality before using this output (e.g.,
implement the sticky nature of an unlock condition by routing it through an external set/reset flip-flop).
By integrating the loop filter and making it programmable, the user can trade off both at runtime depending on the
quality of the incoming HS signal (inaccurate frequency, jitter content).
The filtered phase/frequency error value is now used to correct the programmed nominal DTO increment (NOM_INC
register value). This updated DTO increment (DTO_INC register value) is used by the DTO and determines the
instantaneous DTO output frequency. By making DTO_INC available as a read-only register, the user can read out
via I²C and calculate the instantaneous frequency of the DTO-generated clock.
Because of the digital nature of the PLL, the loop can be opened while still keeping an accurate frequency output.
Therefore, the PLL can also be used as a frequency synthesizer without any HS reference. This is done by disabling
the PFD (PFD_DISABLE register value). This keeps DTO_INC always equal to NOM_INC, thereby producing a DTO
output frequency always equal to the desired programmed frequency, irrespective of HS.
There is a second option to operate in open loop. In some video/graphics modes, no valid HS is present during a part
of the frame/field period, typically during some lines of the VBI (vertical blanking interval). In order to have an accurate
PLL output clock and avoid clock drift, the PFD output needs to be held constant during this time. The PFD FREEZE
pin provides this option. Asserting this pin freezes DTO_INC to its present value, thereby producing a constant PLL
output clock frequency, not necessarily equal to the nominal desired frequency programmed by NOM_INC. Together
with the composite sync slicer, this feature allows using the PLL with input signals containing embedded composite
sync with minimal external logic. See the Composite Sync Slicer section.
The phase of the PLL generated clock can be programmed in 31 uniform steps over a single clock period
(360/31 = 11.6 degrees phase resolution) so that the sampling phase of the ADC can be accurately controlled.
In addition to sourcing the ADC channel clock from the PLL, an external pixel clock can be used (from terminal
EXT_ADCCLK). If configured this way (via SEL_ADCCLK register value), a clock signal of the required sampling
frequency should be applied to EXT_ADCCLK; this signal, instead of the PLL generated clock, is routed to the ADC
channels. In this case no phase control is available on the external clock signal. Still, the internal PLL can be used
and its output made available externally as explained below. This means two clock domains can be implemented on
the THS8083A: one is externally fed, and the other, possibly asynchronous to the first, generated by the internal PLL.
This provides considerable flexibility in the design of video/graphics equipment that implements scaling and frame
rate conversion.
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